US4387341A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multi-purpose retimer driver
Assignee: Lockheed Martin Corp
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Filing: 1981-05-13
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Granted: 1983-06-07
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Expires: 2001-05-13
Abstract
Abstract A general purpose retiming circuit comprising a timing signal source for generating timing signals, a plurality of N registers arranged in a row in a given order with each register having an input terminal, an output terminal, and clock input terminal and responsive to timing signals supplied thereto to transfer the signal supplied to said input terminal means to said output terminal. There is provided a serial input terminal for supplying a serial input signal thereto. Also provided are N switches arranged in the given order and each having first and second input terminals and an output terminal which is connected to the input terminal of a corresponding register of said row of N registers, and with the first input terminal of a first of the N switches being connected to the serial input terminal and the first input terminal of each of the remainder of the N switches being connected to the output terminal of the register preceding the corresponding register in the row of registers. Further provided in logic for supplying an N bit input signal in parallel manner to the second input terminals of the N switches. The N switches are actuated under control of timing signals generated by the timing signal source to selectively connect the first or second input terminals thereof to the output terminal thereof. Still further provided are N parallel output terminals, serial output terminals and a logic circuit responsive to timing signals generated by the timing signal source to selectively connect the output terminals of the N registers to the N parallel output terminals, the second input terminals of the N switches to the N parallel output terminals, and the output terminal of a selected register in the row of N registers to the serial output terminal.
Inventors
- 👤 Lloyd W. Martinson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 23:35
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/15; H03K5/15013; H03K5/1502
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
376 words
A retiming circuit comprising: a clock pulse source for generating clock pulses; a plurality of N registers arranged in a given successive order with each register having an input terminal, an output terminal, and clock input terminal means responsive to clock pulses supplied thereto to transfer the signal supplied to said input terminal to said output terminal; a serial input terminal and means for supplying a serial input signal thereto; N first switches each having first and second input terminals and an output terminal which is connected to the input terminal of a corresponding first register of said N registers, and with the first input terminal of the first switch of said N first switches being connected to said serial input terminal and the first input terminal of each of the remainder of said N switches being connected to the output terminal of the register preceding said corresponding register in said row of registers; means for supplying an N bit input signal in parallel manner to the second input terminals of said N first switches; means for providing timing control signals; said N first switches responsive to said timing control signals to selectively connect the first or second input terminals thereof to the output terminal thereof; N parallel output terminals; serial output terminal; and logic means for selectively connecting the output terminals of said N registers to said N parallel output terminals and the output terminal of a selected register in said N registers to said serial output terminals; said logic means comprising N second switches each corresponding to one of said N registers and arranged in said given successive order and each having first and second input terminals and an output terminal with the first input terminal of each of said second switches being connected to the second input terminal of the corresponding first switch and with the second input terminal thereof being connected to the output terminal of the corresponding register; said logic means further comprising gating means connecting said output terminals of said second switching means to said N parallel output terminals; and said second switching means responsive to said timing control signals to selectively connect said first or second input terminals of each of said second switches to the output terminal thereof.
Claim 2
Dependent Claim
376 words
A retiming circuit comprising: a clock pulse source for generating clock pulses; a plurality of N registers arranged in a given successive order with each register having an input terminal, an output terminal, and clock input terminal means responsive to clock pulses supplied thereto to transfer the signal supplied to said input terminal to said output terminal; a serial input terminal and means for supplying a serial input signal thereto; N first switches each having first and second input terminals and an output terminal which is connected to the input terminal of a corresponding first register of said N registers, and with the first input terminal of the first switch of said N first switches being connected to said serial input terminal and the first input terminal of each of the remainder of said N switches being connected to the output terminal of the register preceding said corresponding register in said row of registers; means for supplying an N bit input signal in parallel manner to the second input terminals of said N first switches; means for providing timing control signals; said N first switches responsive to said timing control signals to selectively connect the first or second input terminals thereof to the output terminal thereof; N parallel output terminals; serial output terminal; and logic means for selectively connecting the output terminals of said N registers to said N parallel output terminals and the output terminal of a selected register in said N registers to said serial output terminals; said logic means comprising N second switches each corresponding to one of said N registers and arranged in said given successive order and each having first and second input terminals and an output terminal with the first input terminal of each of said second switches being connected to the second input terminal of the corresponding first switch and with the second input terminal thereof being connected to the output terminal of the corresponding register; said logic means further comprising gating means connecting said output terminals of said second switching means to said N parallel output terminals; and said second switching means responsive to said timing control signals to selectively connect said first or second input terminals of each of said second switches to the output terminal thereof.
Claim 3
Dependent Claim
190 words
A retiming circuit comprising: a clock pulse source for generating clock pulses; N register means arranged in a given successive order with each register means having input terminal means, and output terminal means, and clock input terminal means responsive to a clock pulse signal supplied thereto to transfer the signal supplied to said input terminal means thereof to said output terminal means thereof; N parallel input terminals; N first switching means for selectively connecting said N parallel input terminals individually to the said input terminal means of said N register means or alternatively to connect the output terminal means of each register means to the said input terminal means of the next successive register means in said given order of register means; and logic means for selectively receiving in parallel manner the output signals appearing on the output terminal means of said N register means or the signals appearing on the output terminal of a selected register means of said N register means when said N first switching means is connecting the output terminal means of said each register means to the input means of the next successive register means.
Claim 4
Dependent Claim
190 words
A retiming circuit comprising: a clock pulse source for generating clock pulses; N register means arranged in a given successive order with each register means having input terminal means, and output terminal means, and clock input terminal means responsive to a clock pulse signal supplied thereto to transfer the signal supplied to said input terminal means thereof to said output terminal means thereof; N parallel input terminals; N first switching means for selectively connecting said N parallel input terminals individually to the said input terminal means of said N register means or alternatively to connect the output terminal means of each register means to the said input terminal means of the next successive register means in said given order of register means; and logic means for selectively receiving in parallel manner the output signals appearing on the output terminal means of said N register means or the signals appearing on the output terminal of a selected register means of said N register means when said N first switching means is connecting the output terminal means of said each register means to the input means of the next successive register means.
Claim 5
Dependent Claim
49 words
A retiming circuit as in claim 2 in which said logic means further comprises: N parallel output terminals; and N second switching means for selectively connecting the said N parallel output terminals to the N output terminals of said N register means or to the N parallel input terminals.
Claim 6
Dependent Claim
44 words
A retiming circuit as in claim 2 and further comprising: S signal sources for each input terminal of said N parallel input terminals; and third switching means for selectively connecting similar signal sources of said S signal sources to said N parallel input terminals.
Claim 7
Dependent Claim
295 words
A retiming circuit comprising: a timing signal source for generating timing signals; a plurality of N registers arranged in a row in a given successive order with each register having input terminal means, output terminal means, and clock input terminal means, and responsive to timing signals supplied to said clock input terminal means to transfer the signal supplied to said input terminal means to said output terminal means; serial input terminal means and means for supplying a serial input signal thereto; N first switches arranged in said given order and each having first and second input terminals and an output terminal which is connected to the input terminal means of a corresponding register of said row of N registers, and with the first input terminal of a particular first switch being connected to said serial input terminal means and the first input terminal of each of the remainder of said N first switches being connected to the output terminal means of the register preceding said corresponding register in said row of registers; means for supplying an N bit input signal in parallel manner to the second input terminal of said N first switches; means for actuating said N first switches under control of timing signals generated by said timing signal source to selectively connect the first or second input terminals thereof to the output terminals thereof; N parallel output terminals; serial output terminal means; and logic means responsive to timing signals generated by said timing signal source to selectively connect the output terminals of said N registers to said N parallel output terminals, the second input terminals of said N first switches to said parallel output terminals, or the output terminal of a selected register of said N registers to said serial output terminal means.
Claim 8
Dependent Claim
295 words
A retiming circuit comprising: a timing signal source for generating timing signals; a plurality of N registers arranged in a row in a given successive order with each register having input terminal means, output terminal means, and clock input terminal means, and responsive to timing signals supplied to said clock input terminal means to transfer the signal supplied to said input terminal means to said output terminal means; serial input terminal means and means for supplying a serial input signal thereto; N first switches arranged in said given order and each having first and second input terminals and an output terminal which is connected to the input terminal means of a corresponding register of said row of N registers, and with the first input terminal of a particular first switch being connected to said serial input terminal means and the first input terminal of each of the remainder of said N first switches being connected to the output terminal means of the register preceding said corresponding register in said row of registers; means for supplying an N bit input signal in parallel manner to the second input terminal of said N first switches; means for actuating said N first switches under control of timing signals generated by said timing signal source to selectively connect the first or second input terminals thereof to the output terminals thereof; N parallel output terminals; serial output terminal means; and logic means responsive to timing signals generated by said timing signal source to selectively connect the output terminals of said N registers to said N parallel output terminals, the second input terminals of said N first switches to said parallel output terminals, or the output terminal of a selected register of said N registers to said serial output terminal means.
Claim 9
Dependent Claim
106 words
A retiming circuit as in claim 5 in which said logic means comprises: N second switching means each corresponding to one of said N registers and each having first and second input terminals and an output terminal with the first input terminal thereof being connected to the second input terminal of the corresponding switch of said N first switches and with the second input terminal thereof being connected to the output terminal means of the corresponding register; and gating means responsive to timing signals from said timing signal source to connect the output terminals of said N second switching means to said N parallel output terminals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-06-06 | 1986-12-06 | 1987-06-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-06-06 | 1990-12-06 | 1991-06-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-06-06 | 1994-12-06 | 1995-06-07 | $7700.00 | Window Closed / Lapsed |