Information transfer system

Claim 2

An information transfer system comprising: a first storage unit containing binary information, a second storage unit, a variable energizing source, transfer means including an intermediate storage unit responsive to said variable energizing source for transferring binary information from said first storage unit to said second storage unit, said transfer means including gate means responsive to one condition of said variable energizing source for transferring said binary information from said first storage unit to said intermediate storage unit, while blocking the transfer of binary information into said second storage unit and responsive to a different condition of said energizing source for transferring said binary information from said intermediate storage unit into said second storage unit while blocking the transfer of binary information from said first storage unit into said intermediate storage unit and nonresponsive to said energizing source when it is changing from said one condition to said different condition and wherein said first storage unit comprises first and second transistors, the collector of said first transistor being directly connected to the base of said second transistor, the collector of said second transistor being directly connected to the base of said first transistor, the emitters of said first and second transistor being connected together, said intermediate storage unit comprising third and fourth transistors, the collector of said third transistor being directly connected to the base of said fourth transistor, the collector of said fourth transistor being directly connected to the base of said third transistor, and the emitters of said third and fourth transistors being connected to said variable energizing source, said second storage unit comprising fifth and sixth transistors, the collector of said sixth transistor being directly connected to the base of said sixth transistor, the collector of said sixth transistor being directly connected to the base of said fifth transistor, and the emitters of said fifth and sixth transistors being connected together, and a biasing voltage being connected to the collectors of said transistors.

Claim 3

An information transfer system comprising a first storage unit containing binary information, said first storage unit comprising first and second transistors, the collector of said first transistor being directly connected to the base of said second transistor, the collector of said second transIstor being directly connected to the base of said first transistor and the emitters of said first and second transistors being connected together, a second storage unit comprising third and fourth transistors, the collector of said third transistor being directly connected to the base of said fourth transistor, the collector of said fourth transistor being directly connected to the base of said third transistor, and the emitters of said third and fourth transistors being connected together, a variable energizing source, transfer means including an intermediate storage unit responsive to said variable energizing source for transferring binary information from said first storage unit to said second storage unit, said transfer means including gate means responsive to one condition of said variable energizing source for transferring said binary information from said first storage unit to said intermediate storage unit while blocking the transfer of binary information into said second storage unit and responsive to a different condition of said energizing source for transferring said binary information from said intermediate storage unit into said second storage unit while blocking the transfer of binary information from said first storage unit into said intermediate storage unit and nonresponsive to said energizing source when it is changing from said one condition to said different condition, said intermediate storage unit comprising fifth and sixth transistors, the collector of said fifth transistor being directly connected to the base of said sixth transistor, the collector of said sixth transistor being directly connected to the base of said fifth transistor and the emitters of said fifth and sixth transistors being connected to said variable energizing source and wherein said gate means comprises a first asymmetrically conductive means directly coupled between the collector of said first transistor and the collector of said third transistor, a second asymmetrically conductive means directly coupled between the collector of said second transistor and the collector of said fourth transistor, a third asymmetrically conductive means connected between the collector of said third transistor and the collector of said fifth transistor, and a fourth asymmetrically conductive means connected between the collector of said fourth transistor and the collector of said sixth transistor.

Claim 4

An information transfer system comprising a first storage unit containing binary information, said first storage unit comprising first and second transistors, the collector of said first transistor being directly connected to the base of said second transistor, the collector of said second transIstor being directly connected to the base of said first transistor and the emitters of said first and second transistors being connected together, a second storage unit comprising third and fourth transistors, the collector of said third transistor being directly connected to the base of said fourth transistor, the collector of said fourth transistor being directly connected to the base of said third transistor, and the emitters of said third and fourth transistors being connected together, a variable energizing source, transfer means including an intermediate storage unit responsive to said variable energizing source for transferring binary information from said first storage unit to said second storage unit, said transfer means including gate means responsive to one condition of said variable energizing source for transferring said binary information from said first storage unit to said intermediate storage unit while blocking the transfer of binary information into said second storage unit and responsive to a different condition of said energizing source for transferring said binary information from said intermediate storage unit into said second storage unit while blocking the transfer of binary information from said first storage unit into said intermediate storage unit and nonresponsive to said energizing source when it is changing from said one condition to said different condition, said intermediate storage unit comprising fifth and sixth transistors, the collector of said fifth transistor being directly connected to the base of said sixth transistor, the collector of said sixth transistor being directly connected to the base of said fifth transistor and the emitters of said fifth and sixth transistors being connected to said variable energizing source and wherein said gate means comprises a first asymmetrically conductive means directly coupled between the collector of said first transistor and the collector of said third transistor, a second asymmetrically conductive means directly coupled between the collector of said second transistor and the collector of said fourth transistor, a third asymmetrically conductive means connected between the collector of said third transistor and the collector of said fifth transistor, and a fourth asymmetrically conductive means connected between the collector of said fourth transistor and the collector of said sixth transistor.

Claim 5

An information transfer system according to claim 2 wherein said first, second, third and fourth asymmetrically conductive means each comprise a transistor having its base and collector electrodes connected together.

Claim 6

An information transfer system comprising a semiconductor wafer, a first storage unit containing binary information formed at one surface of said semiconductor wafer, a second storage unit formed at said one surface of said semiconductor wafer, a variable energizing source, transfer means formed at said one surface of said semiconductor wafer, said transfer means including an intermediate storage unit responsive to said variable energizing source for transferring binary information from said first storage unit to said second storage unit, said transfer means including gate means responsive to one condition of said variable energizing source for transferring said binary information from said first storage unit to said intermediate storage unit while blocking the transfer of binary information into said second storage unit and responsive to a different condition of said energizing source for transferring said binary information from said intermediate storage unit into said second storage unit while blocking the transfer of binary information from said first storage unit into said intermediate storage unit and nonresponsive to said energizing source when it is changing from said one condition to said different condition and wherein said first storage unit, said second storage unit and said intermediate unit each comprise a direct coupled collector to base triple diffused transistors in said semiconductor wafer and said gate means comprises a triple diffused transistor in said semiconductor wafer having its base and collector electrodes connected together and being directly connected between the collectors of transistors in different storage units.

Claim 7

An information transfer system comprising a semiconductor wafer, a first storage unit containing binary information formed at one surface of said semiconductor wafer, a second storage unit formed at said one surface of said semiconductor wafer, a variable energizing source, transfer means formed at said one surface of said semiconductor wafer, said transfer means including an intermediate storage unit responsive to said variable energizing source for transferring binary information from said first storage unit to said second storage unit, said transfer means including gate means responsive to one condition of said variable energizing source for transferring said binary information from said first storage unit to said intermediate storage unit while blocking the transfer of binary information into said second storage unit and responsive to a different condition of said energizing source for transferring said binary information from said intermediate storage unit into said second storage unit while blocking the transfer of binary information from said first storage unit into said intermediate storage unit and nonresponsive to said energizing source when it is changing from said one condition to said different condition and wherein said first storage unit, said second storage unit and said intermediate unit each comprise a direct coupled collector to base triple diffused transistors in said semiconductor wafer and said gate means comprises a triple diffused transistor in said semiconductor wafer having its base and collector electrodes connected together and being directly connected between the collectors of transistors in different storage units.

Claim 8

An information transfer system comprising a semiconductor wafer, a first storage unit containing binary information formed at one surface of said semiconductor wafer, a second storage unit formed at said one surface of said semiconductor wafer, a variable energizing source, transfer means formed at said one surface of said semiconductor wafer, said transfer means including an intermediate storage unit responsive to said variable energizing source for transferring binary information from said first storage unit to said second storage unit, said transfer means including gate means responsive to one condition of said variable energizing source for transferring said binary information from said first storage unit to said intermediate storage unit while blocking the transfer of binary information into said second storage unit and responsive to a different condition of said energizing source for transferring said binary information from said intermediate storage unit into said second storage unit while blocking the transfer of binary information from said first storage unit into said intermediate storage unit and nonresponsive to said energizing source when it is changing from said one condition to said different condition and wherein said semiconductor wafer comprises a semiconductor substrate of one conductivity type and an epitaxial layer of opposite conductivity type on said semiconductor substrate, said first and second storage unit and said intermediate storage unit each comprise direct coupled collector to base double diffused multiemitter transistors formed in said epitaxial layer said gate means comprises an emitter electrode of each of said multiemitter transistors in said second and intermediate storage units and is coupled to the collector electrode of a multiemitter transistor in a preceding storage unit.

Claim 9

An information transfer system comprising a semiconductor wafer, a first storage unit containing binary information formed at one surface of said semiconductor wafer, a second storage unit formed at said one surface of said semiconductor wafer, a variable energizing source, transfer means formed at said one surface of said semiconductor wafer, said transfer means including an intermediate storage unit responsive to said variable energizing source for transferring binary information from said first storage unit to said second storage unit, said transfer means including gate means responsive to one condition of said variable energizing source for transferring said binary information from said first storage unit to said intermediate storage unit while blocking the transfer of binary information into said second storage unit and responsive to a different condition of said energizing source for transferring said binary information from said intermediate storage unit into said second storage unit while blocking the transfer of binary information from said first storage unit into said intermediate storage unit and nonresponsive to said energizing source when it is changing from said one condition to said different condition and wherein said semiconductor wafer comprises a semiconductor substrate of one conductivity type and an epitaxial layer of opposite conductivity type on said semiconductor substrate, said first and second storage unit and said intermediate storage unit each comprise direct coupled collector to base double diffused multiemitter transistors formed in said epitaxial layer said gate means comprises an emitter electrode of each of said multiemitter transistors in said second and intermediate storage units and is coupled to the collector electrode of a multiemitter transistor in a preceding storage unit.

Claim 10

An information transfer system comprising: a first storage unit containing binary information, a second storage unit, a variable energizing source, transfer means including an intermediate storage unit responsive to said variable energizing source for transferring binary information from said first storage unit to said second storage unit, said transfer means including gate means responsive to one condition of said variable energizing source for transferring said binary information from said first storage unit to said intermediate storage unit, while blocking the transfer of binary information into said second storage unit and responsive to a different condition of said energizing source for transferring said binary information from said intermediate storage unit into said second storage unit while blocking the transfer of binary information from said first storage unit into said intermediate storage unit and nonresponsive to said energizing source when it is changing from said one condition to said different condition and wherein said first storage unit comprises first and second transistors, the collector of said first transistor being directly connected to the base of said second transistor, the collector of said second transistor being directly connected to the base of said first transistor, the emitters of said first and second transistor being connected together, said intermediate storage unit comprising third and fourth multiemitter transistors, the collector of said third transistor being directly connected to the base of said fourth transistor, the collector of said fourth transistor being directly connected to the base of said third transistor, and one of the emitters of said third and fourth transistors being connected to said variable energizing source, said second storage unit comprising fifth and sixth multiemitter transistors, the collector of said sixth transistor being directly Pg,23 connected to the base of said sixth transistor, the collector of said sixth transistor being directly connected to the base of said fifth transistor, and one of the emitters of said fifth and sixth transistors being connected together, said gate means comprising another emitter of said third, fourth, fifth and sixth transistors and a biasing voltage being connected to the collectors of said transistors.

Claim 11

An information transfer system comprising: a first storage unit containing binary information, a second storage unit, a variable energizing source, transfer means including an intermediate storage unit responsive to said variable energizing source for transferring binary information from said first storage unit to said second storage unit, said transfer means including gate means responsive to one condition of said variable energizing source for transferring said binary information from said first storage unit to said intermediate storage unit, while blocking the transfer of binary information into said second storage unit and responsive to a different condition of said energizing source for transferring said binary information from said intermediate storage unit into said second storage unit while blocking the transfer of binary information from said first storage unit into said intermediate storage unit and nonresponsive to said energizing source when it is changing from said one condition to said different condition and wherein said first storage unit comprises first and second transistors, the collector of said first transistor being directly connected to the base of said second transistor, the collector of said second transistor being directly connected to the base of said first transistor, the emitters of said first and second transistor being connected together, said intermediate storage unit comprising third and fourth multiemitter transistors, the collector of said third transistor being directly connected to the base of said fourth transistor, the collector of said fourth transistor being directly connected to the base of said third transistor, and one of the emitters of said third and fourth transistors being connected to said variable energizing source, said second storage unit comprising fifth and sixth multiemitter transistors, the collector of said sixth transistor being directly Pg,23 connected to the base of said sixth transistor, the collector of said sixth transistor being directly connected to the base of said fifth transistor, and one of the emitters of said fifth and sixth transistors being connected together, said gate means comprising another emitter of said third, fourth, fifth and sixth transistors and a biasing voltage being connected to the collectors of said transistors.

Claim 12

An information transfer system comprising a first storage unit containing binary information, said first storage unit comprising first and second multiemitter transistors, the collector of said first transistor being directly connected to the base of said second transistor, the collector of said second transistor being directly connected to the base of said first transistor and one of the emitters of said first and second transistors being connected together, a second storage unit comprising third and fourth multiemitter transistors, the collector of said third transistor being directly connected to the base of said fourth transistor, the collector of said fourth transistor being directly connected to the base of sad third transistor, and one of the emitters of said third and fourth transistors being connected together, a variable energizing source, transfer means including an intermediate storage unit responsive to said variable energizing source for transferring binary information from said first storage unit to said second storage unit said transfer means including gate means responsive to one condition of said variable energizing source for transferring said binary information from said first storage unit to said intermediate storage unit while blocking the transfer of binary information into said second storage unit and responsive to a different condition of said energizing source for transferring said binary information from said intermediate storage unit into said second storage unit while blocking the transfer of binary information from said first storage unit into said intermediate storage unit and nonresponsive to said energizing source when it is changing from said one condition to said different condition, said intermediate storage unit comprising fifth and sixth multiemitter transistors, the collector of said fifth transistor being directly connected to the base of said sixth transistor, the collector of said sixth transistor being directly connected to the base of said fifth transistor and one of the emitters of said fifth and sixth transistors being connected to said variable energizing source and wherein said gate means comprises another emitter of said third transistor coupled to the collector of said first transistor another emitter of said fourth transistor coupled to the collector of said second transistor another emitter of said fifth transistor connected to the collector of said third transistor and another emitter of said sixth transistor connected to the collector of said fourth transistor.

Claim 13

An information transfer system comprising a first storage unit containing binary information, said first storage unit comprising first and second multiemitter transistors, the collector of said first transistor being directly connected to the base of said second transistor, the collector of said second transistor being directly connected to the base of said first transistor and one of the emitters of said first and second transistors being connected together, a second storage unit comprising third and fourth multiemitter transistors, the collector of said third transistor being directly connected to the base of said fourth transistor, the collector of said fourth transistor being directly connected to the base of sad third transistor, and one of the emitters of said third and fourth transistors being connected together, a variable energizing source, transfer means including an intermediate storage unit responsive to said variable energizing source for transferring binary information from said first storage unit to said second storage unit said transfer means including gate means responsive to one condition of said variable energizing source for transferring said binary information from said first storage unit to said intermediate storage unit while blocking the transfer of binary information into said second storage unit and responsive to a different condition of said energizing source for transferring said binary information from said intermediate storage unit into said second storage unit while blocking the transfer of binary information from said first storage unit into said intermediate storage unit and nonresponsive to said energizing source when it is changing from said one condition to said different condition, said intermediate storage unit comprising fifth and sixth multiemitter transistors, the collector of said fifth transistor being directly connected to the base of said sixth transistor, the collector of said sixth transistor being directly connected to the base of said fifth transistor and one of the emitters of said fifth and sixth transistors being connected to said variable energizing source and wherein said gate means comprises another emitter of said third transistor coupled to the collector of said first transistor another emitter of said fourth transistor coupled to the collector of said second transistor another emitter of said fifth transistor connected to the collector of said third transistor and another emitter of said sixth transistor connected to the collector of said fourth transistor.