US5119331A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Segmented flash write
Assignee: Renesas Electronics America Inc
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Filing: 1990-09-04
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Granted: 1992-06-02
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Expires: 2010-09-04
Abstract
Abstract A method in which a variable sized segment of a memory array can be written in a single memory cycle is provided. A predetermined set of the column addresses or a combination of the column address and I/O field specify the starting location of a block of a memory array row to be written. The set of remaining column addresses specifies displacement from the starting location. Together the starting segment and the displacement define an area of memory which can be written in a single cycle.
Inventors
- 👤 Howard H. Sussman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 03:36
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1015
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
107 words
A method for writing a block of data bits to a line of a memory array, said memory array having a plurality of lines for storing data bits, each line having a plurality of addresses associated therewith, said method comprising the steps of: providing a first subset of addresses for designating a starting location of said line; providing a second subset of addresses for designating a displacement along said line; enabling said first subset of addresses and said second subset of addresses to designate a portion of said line; and writing a plurality of data bits to said portion of said line, each data bit being identical.
Claim 2
Independent Claim
107 words
A method for writing a block of data bits to a line of a memory array, said memory array having a plurality of lines for storing data bits, each line having a plurality of addresses associated therewith, said method comprising the steps of: providing a first subset of addresses for designating a starting location of said line; providing a second subset of addresses for designating a displacement along said line; enabling said first subset of addresses and said second subset of addresses to designate a portion of said line; and writing a plurality of data bits to said portion of said line, each data bit being identical.
Claim 3
Independent Claim
141 words
A method for writing a block of data bits to a row of a memory array on a memory device, said memory array having a plurality of rows for storing data bits, said memory array also having a plurality of column locations, each column location having a plurality of addresses associated therewith, said memory device having a plurality of data lines operatively connected to said column locations, said method comprising the steps of: providing a first subset of addresses for designating a starting location of said row; providing a second subset of addresses for designating a displacement along said row; enabling said first subset of addresses and said second subset of addresses to designate a portion of said row; and writing a plurality of data bits from said data lines to said portion of said row, each data bit being identical.
Claim 4
Independent Claim
141 words
A method for writing a block of data bits to a row of a memory array on a memory device, said memory array having a plurality of rows for storing data bits, said memory array also having a plurality of column locations, each column location having a plurality of addresses associated therewith, said memory device having a plurality of data lines operatively connected to said column locations, said method comprising the steps of: providing a first subset of addresses for designating a starting location of said row; providing a second subset of addresses for designating a displacement along said row; enabling said first subset of addresses and said second subset of addresses to designate a portion of said row; and writing a plurality of data bits from said data lines to said portion of said row, each data bit being identical.
Claim 5
Dependent Claim
26 words
The method according to claim 2 wherein said data lines are combined with said first subset of addresses for designating a starting location of said row.
Claim 6
Dependent Claim
25 words
The method according to claim 2 wherein said data lines are combined with said second subset of addresses for designating a displacement along said row.
References Cited (Backward Citations)
US4879692A
Cited
US5003510A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-06-02 | 1995-12-02 | 1996-06-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-06-02 | 1999-12-02 | 2000-06-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-06-02 | 2003-12-02 | 2004-06-02 | $7700.00 | Window Closed / Lapsed |