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US5508555A
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Thin film field effect transistor having a doped sub-channel region
Assignee: US Philips Corp
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Filing: 1995-06-06
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Granted: 1996-04-16
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Expires: 2015-06-06
Abstract
Abstract A thin film field effect transistor (1) is formed by an insulating substrate (2,3) carrying a semiconductor layer (4) having a polycrystalline channel region (5) which is passivated to reduce the density of charge carrier traps. Source and drain electrodes (6 and 7) contact opposite ends (5a,5b) of the channel region (5), and a gate electrode (8) is provided at one major surface (4a) of the semiconductor layer (4) for controlling a conduction channel of one conductivity type in the polycrystalline channel region (5) to provide a gateable connection between the source and drain electrodes (6 and 7). An area (50) of the polycrystalline channel region (5) spaced from the electrodes (6,7,8) of the transistor (1) and lying adjacent to the other major surface (4b) of the semiconductor layer (4) is doped with impurities of the opposite conductivity type for suppressing formation of a conduction channel of the one conductivity type adjacent to the other major surface (4b).
Inventors
- 👤 Stanley D. Brotherton
- 👤 John R. A. Ayres
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 12:33
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6704; H10D30/6706; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0314; H10D30/6729; H10D30/673; H10D30/6731; H10D30/6757
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
139 words
A thin film field effect transistor comprising (a) an insulating substrate, (b) a polycrystalline semiconductor layer disposed on said insulating substrate, (c) a channel region disposed in said polycrystalline semiconductor layer, said channel region forming a conduction channel of a first conductivity type, (d) a gate electrode structure disposed on said channel region, (e) source and drain electrode structures disposed at opposite sides of said gate electrode structure and at opposite ends of said channel region, and (f) layer means disposed in said polycrystalline semiconductor layer between said insulating substrate and said channel region and extending between said source and drain electrode structures for suppressing formation of said conduction channel of said first conductivity type at said insulating substrate, said layer means being doped with impurities of a second conductivity type to reduce leakage current at said insulating substrate.
Claim 2
Dependent Claim
139 words
A thin film field effect transistor comprising (a) an insulating substrate, (b) a polycrystalline semiconductor layer disposed on said insulating substrate, (c) a channel region disposed in said polycrystalline semiconductor layer, said channel region forming a conduction channel of a first conductivity type, (d) a gate electrode structure disposed on said channel region, (e) source and drain electrode structures disposed at opposite sides of said gate electrode structure and at opposite ends of said channel region, and (f) layer means disposed in said polycrystalline semiconductor layer between said insulating substrate and said channel region and extending between said source and drain electrode structures for suppressing formation of said conduction channel of said first conductivity type at said insulating substrate, said layer means being doped with impurities of a second conductivity type to reduce leakage current at said insulating substrate.
Claim 3
Dependent Claim
19 words
A thin film field effect transistor as claimed in claim 1, wherein said polycrystalline semiconductor layer is polycrystalline silicon.
Claim 4
Dependent Claim
21 words
A thin film field effect transistor as claimed in claim 2, wherein said layer means is polycrystalline silicon doped with boron.
Claim 5
Dependent Claim
20 words
A thin film field effect transistor according to claim 3, wherein said channel region is polycrystalline silicon passivated with hydrogen.
Claim 6
Dependent Claim
41 words
A thin film field effect transistor as claimed in claim 4, wherein highly doped contact regions are disposed at each end of said channel region to provide an ohmic contact respectively with said source electrode structure and said drain electrode structure.
Claim 7
Dependent Claim
147 words
A thin film field effect transistor comprising (a) an insulating glass substrate, (b) a polycrystalline silicon layer disposed on said glass substrate, (c) an intrinsic channel region disposed in said polycrystalline silicon layer, said channel region being passivated with hydrogen and providing a conduction channel of a first conductivity type, (d) an insulated gate electrode structure disposed on said channel region, (e) source and drain electrode structures disposed at opposite sides of said insulated gate electrode structure and at opposite ends of said channel region, and (f) a layer doped with impurities of a second conductivity type and extending in said polycrystalline silicon layer between the source and drain electrodes, said layer separating said glass substrate from said channel region to suppress formation of said conduction channel of said first conductivity type adjacent to said glass substrate in order to reduce leakage currents at said glass substrate.
Claim 8
Dependent Claim
147 words
A thin film field effect transistor comprising (a) an insulating glass substrate, (b) a polycrystalline silicon layer disposed on said glass substrate, (c) an intrinsic channel region disposed in said polycrystalline silicon layer, said channel region being passivated with hydrogen and providing a conduction channel of a first conductivity type, (d) an insulated gate electrode structure disposed on said channel region, (e) source and drain electrode structures disposed at opposite sides of said insulated gate electrode structure and at opposite ends of said channel region, and (f) a layer doped with impurities of a second conductivity type and extending in said polycrystalline silicon layer between the source and drain electrodes, said layer separating said glass substrate from said channel region to suppress formation of said conduction channel of said first conductivity type adjacent to said glass substrate in order to reduce leakage currents at said glass substrate.
References Cited (Backward Citations)
US3958266A
Cited
US4496963A
Cited
US4199773A
Cited
JPS55148464A
Cited
US5021843A
Cited
JPS6122669A
Cited
US5055895A
Cited
JPH01241854A
Cited
US5040037A
Cited
US5031008A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1999-04-16 | 1999-10-16 | 2000-04-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-04-16 | 2003-10-16 | 2004-04-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-04-16 | 2007-10-16 | 2008-04-16 | $7700.00 | Window Closed / Lapsed |