Semiconductor integrated circuit

Claim 2

A semiconductor integrated circuit comprising an insulated-gate transistor serving as a driving transistor and composed of source and drain regions of one conductivity type and a high impurity concentration, a channel region disposed between said source and drain regions, an insulating layer covering almost the entire surface of said channel region except for portions adjacent to said source and drain regions, at least one portion of said insulating layer being thinner than the remainder of said insulating layer, a gate electrode of a conductive material disposed adjacent said thinner portion of said insulating layer for maintaining said channel region substantially in floating condition, and a high resistivity region disposed adjacent said channel region and electrically connected to said source region, said high resistivity region being of the same conductivity type as said channel region, the resistance R cs of said high resistivity region satisfying the relations of R cs ·C cs >>τ.sub.γ and R cs ·C cs ≦τ wherein, τ=the period of a high frequency pulse voltage supplied to said gate electrode; τ.sub.γ =the rise time of a high frequency pulse voltage supplied to said gate electrode; and C cs =the capacitance of the channel and source regions.

Claim 3

A semiconductor integrated circuit of claim 1 wherein the impurity concentration N of the channel region has a relation of N<D -3 with respect to the depth D of the channel region.

Claim 4

A semiconductor integrated circuit comprising an insulated-gate transistor serving as a driving transistor and composed of source and drain regions of one conductivity type and a high impurity concentration, a channel region disposed between said source and drain regions, an insulating layer covering almost the entire surface of said channel region except for portions adjacent to said source and drain regions, at least two portions of said insulating layer being thinner than the remainder of said insulating layer, at least two gate electrodes of a conductive material disposed adjacent said thinner portions of said insulating layer for maintaining said channel region substantially in floating condition, and a high resistivity region disposed adjacent said channel region and electrically connected to said source region, said high resistivity region being of the same conductivity type as said channel region, the resistance R cs of said high resistivity region satisfying the relations of R cs ·C cs >>τ.sub.γ and R cs ·C cs ≦τ wherein, τ=the period of a high frequency pulse voltage supplied to said gate electrodes; τ.sub.γ =the rise time of a high frequency pulse voltage supplied to said gate electrodes; and C cs =the capacitance of the channel and source regions.

Claim 5

A semiconductor integrated circuit comprising an insulated-gate transistor serving as a driving transistor and composed of source and drain regions of one conductivity type and a high impurity concentration, a channel region disposed between said source and drain regions, an insulating layer covering almost the entire surface of said channel region except for portions adjacent to said source and drain regions, at least two portions of said insulating layer being thinner than the remainder of said insulating layer, at least two gate electrodes of a conductive material disposed adjacent said thinner portions of said insulating layer for maintaining said channel region substantially in floating condition, and a high resistivity region disposed adjacent said channel region and electrically connected to said source region, said high resistivity region being of the same conductivity type as said channel region, the resistance R cs of said high resistivity region satisfying the relations of R cs ·C cs >>τ.sub.γ and R cs ·C cs ≦τ wherein, τ=the period of a high frequency pulse voltage supplied to said gate electrodes; τ.sub.γ =the rise time of a high frequency pulse voltage supplied to said gate electrodes; and C cs =the capacitance of the channel and source regions.

Claim 6

A semiconductor integrated circuit of claim 3 wherein the impurity concentration N of the channel region has a relation of N<D -3 with respect to the depth D of the channel region.

Claim 7

A semiconductor integrated circuit comprising two complementary insulated-gate transistors of different conductivity types having drain electrodes directly connected to each other and gate electrodes directly connected to each other, the connected gate electrodes serving as an input terminal and the connected drain electrodes serving as an output terminal, each of said insulated-gate transistors being composed of source and drain regions of one conductivity type and a high impurity concentration, a channel region disposed between each of said transistors' source and drain regions, an insulating layer covering almost the entire surface of said channel regions except for portions adjacent to said source and drain regions, at least a portion of said insulating layer being thinner than the remainder of said insulating layer, one of said gate electrodes being composed of a conductive material and disposed adjacent to said thinner portion of said insulating layer for maintaining one of said channel regions substantially in floating condition, and a high resistivity region disposed adjacent said one channel region and electrically connected to one of said source regions, said high resistivity region being of the same conductivity type as said one channel region, the resistance R cs of said high resistivity region satisfying the relations of R cs ·C cs >>τ.sub.γ and R cs ·C cs ≦τ wherein, τ=the period of a high frequency pulse voltage supplied to said connected gate electrodes; τ.sub.γ =the rise time of a high frequency pulse voltage supplied to said connected gate electrodes; and C cs =the capacitance of the channel and source regions.

Claim 8

A semiconductor integrated circuit comprising two complementary insulated-gate transistors of different conductivity types having drain electrodes directly connected to each other and gate electrodes directly connected to each other, the connected gate electrodes serving as an input terminal and the connected drain electrodes serving as an output terminal, each of said insulated-gate transistors being composed of source and drain regions of one conductivity type and a high impurity concentration, a channel region disposed between each of said transistors' source and drain regions, an insulating layer covering almost the entire surface of said channel regions except for portions adjacent to said source and drain regions, at least a portion of said insulating layer being thinner than the remainder of said insulating layer, one of said gate electrodes being composed of a conductive material and disposed adjacent to said thinner portion of said insulating layer for maintaining one of said channel regions substantially in floating condition, and a high resistivity region disposed adjacent said one channel region and electrically connected to one of said source regions, said high resistivity region being of the same conductivity type as said one channel region, the resistance R cs of said high resistivity region satisfying the relations of R cs ·C cs >>τ.sub.γ and R cs ·C cs ≦τ wherein, τ=the period of a high frequency pulse voltage supplied to said connected gate electrodes; τ.sub.γ =the rise time of a high frequency pulse voltage supplied to said connected gate electrodes; and C cs =the capacitance of the channel and source regions.

Claim 9

A semiconductor integrated circuit of claim 5 wherein the impurity concentration N of said one channel region has a relation of N<D -3 with respect to the depth D of said one channel region.

Claim 10

A semiconductor integrated circuit comprising two complementary insulated-gate transistors of different conductivity types having drain electrodes directly connected to each other and gate electrodes directly connected to each other, the connected gate electrodes serving as an input terminal and the connected drain electrodes serving as an output terminal, each of said insulated-gate transistors being composed of source and drain regions of one conductivity type and a high impurity concentration, a channel region disposed between each of said transistors' source and drain regions, an insulating layer covering almost the entire surface of said channel regions except for portions adjacent to said source and drain regions, at least two portions of said insulating layer being thinner than the remainder of said insulating layer, said gate electrodes being composed of a conductive material and respectively disposed adjacent to said respective thinner portions of said insulating layer for maintaining said respective channel regions substantially in floating condition, and a high resistivity region disposed adjacent each of said channel regions and electrically connected to said source regions, said high resistivity regions being of the same conductivity type as said channel regions, the resistance R cs of said high resistivity regions satisfying the relations of R cs ·C cs >>τ.sub.γ and R cs ·C cs ≦τ wherein, τ=the period of a high frequency pulse voltage supplied to said connected gate electrodes; τ.sub.γ =the rise time of a high frequency pulse voltage supplied to said connected gate electrodes; and C cs =the capacitance of the channel and source regions.

Claim 11

A semiconductor integrated circuit comprising two complementary insulated-gate transistors of different conductivity types having drain electrodes directly connected to each other and gate electrodes directly connected to each other, the connected gate electrodes serving as an input terminal and the connected drain electrodes serving as an output terminal, each of said insulated-gate transistors being composed of source and drain regions of one conductivity type and a high impurity concentration, a channel region disposed between each of said transistors' source and drain regions, an insulating layer covering almost the entire surface of said channel regions except for portions adjacent to said source and drain regions, at least two portions of said insulating layer being thinner than the remainder of said insulating layer, said gate electrodes being composed of a conductive material and respectively disposed adjacent to said respective thinner portions of said insulating layer for maintaining said respective channel regions substantially in floating condition, and a high resistivity region disposed adjacent each of said channel regions and electrically connected to said source regions, said high resistivity regions being of the same conductivity type as said channel regions, the resistance R cs of said high resistivity regions satisfying the relations of R cs ·C cs >>τ.sub.γ and R cs ·C cs ≦τ wherein, τ=the period of a high frequency pulse voltage supplied to said connected gate electrodes; τ.sub.γ =the rise time of a high frequency pulse voltage supplied to said connected gate electrodes; and C cs =the capacitance of the channel and source regions.

Claim 12

A semiconductor integrated circuit of claim 7 wherein the impurity concentration N of both said channel regions has a relation of N<D -3 with respect to the depth D of the channel regions.