US5506153A
Expired / Lapsed
US
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Method for manufacture of a controllable power semiconductor element with buffer zone
Assignee: Infineon Technologies AG
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Filing: 1995-06-13
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Granted: 1996-04-09
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Expires: 2015-06-13
Abstract
Abstract Controllable power semiconductor components such as, for example, IGBTs and thyristors are provided, which, compared to known components, have a relatively lightly doped n-buffer zone, a relatively flat p-emitter, and an n-base having a comparatively long charge carrier life expectancy. An advantage is achieved that the controllable power semiconductor component has a temperature-independent tail current, despite a low on-state dc resistance and a high blocking voltage.
Inventors
- 👤 Heinrich Brunner
- 👤 York C. Gerstenmaier
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 05:26
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/141; H10D62/142; H10D12/00; H10D12/411; H10D12/441; H10D18/00; Y; Y10; Y10S; Y10S148/00; Y10S148/012; Y10S148/126
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
121 words
A method for manufacturing a controllable power semiconductor component, comprising the steps of: providing a wafer of n - -doped silicon as a substrate; applying an n-buffer zone onto the substrate by epitaxy; connecting the n-buffer zone to a further silicon wafer by bonding in order to enhance mechanical stability; producing a cathode-side structure in the n - -doped silicon substrate and providing a cathode terminal on the cathode-side structure along with a gate terminal and gate electrode, said n - -doped silicon substrate serving as a base zone; removing said further silicon wafer by grinding; and providing a p-emitter zone adjacent to said n-buffer zone by implantation into said n-buffer zone, and providing an anode terminal at said p-emitter zone.
Claim 2
Independent Claim
121 words
A method for manufacturing a controllable power semiconductor component, comprising the steps of: providing a wafer of n - -doped silicon as a substrate; applying an n-buffer zone onto the substrate by epitaxy; connecting the n-buffer zone to a further silicon wafer by bonding in order to enhance mechanical stability; producing a cathode-side structure in the n - -doped silicon substrate and providing a cathode terminal on the cathode-side structure along with a gate terminal and gate electrode, said n - -doped silicon substrate serving as a base zone; removing said further silicon wafer by grinding; and providing a p-emitter zone adjacent to said n-buffer zone by implantation into said n-buffer zone, and providing an anode terminal at said p-emitter zone.
Claim 3
Dependent Claim
86 words
A method according to claim 1 including the step of providing the n-buffer zone with a thickness between 20 and 80 μm and a doping concentration at an anode-side edge of 8×10 13 through 5×10 14 cm -3 ; providing said p-emitter zone with a thickness of 400-1000 nm and a doping concentration at an anode-side edge of 10 17 through 10 18 cm -3 ; and providing said n - -base zone with a life expectancy of charge carriers that is longer than 10 μsec.
Claim 4
Independent Claim
124 words
A method for manufacturing a controllable power semiconductor component, comprising the steps of: providing a wafer of n - -doped silicon as a substrate; producing an n-buffer zone in the substrate by drive-in of phosphorous atoms; connecting the n-buffer zone to a further silicon wafer by bonding in order to enhance mechanical stability; producing a cathode-side structure in the n - -doped silicon substrate and providing a cathode terminal on the cathode-side structure along with a gate terminal and gate electrode, said n - -doped silicon substrate serving as a base zone; removing said further silicon wafer by grinding; and providing a p-emitter zone adjacent to said n-buffer zone by implantation into said n-buffer zone, and providing an anode terminal at said p-emitter zone.
Claim 5
Independent Claim
124 words
A method for manufacturing a controllable power semiconductor component, comprising the steps of: providing a wafer of n - -doped silicon as a substrate; producing an n-buffer zone in the substrate by drive-in of phosphorous atoms; connecting the n-buffer zone to a further silicon wafer by bonding in order to enhance mechanical stability; producing a cathode-side structure in the n - -doped silicon substrate and providing a cathode terminal on the cathode-side structure along with a gate terminal and gate electrode, said n - -doped silicon substrate serving as a base zone; removing said further silicon wafer by grinding; and providing a p-emitter zone adjacent to said n-buffer zone by implantation into said n-buffer zone, and providing an anode terminal at said p-emitter zone.
Claim 6
Dependent Claim
86 words
A method according to claim 3 including the step of providing the n-buffer zone with a thickness between 20 and 80 μm and a doping concentration at an anode-side edge of 8×10 13 through 5×10 14 cm -3 ; providing said p-emitter zone with a thickness of 400-1000 nm and a doping concentration at an anode-side edge of 10 17 through 10 18 cm -3 ; and providing said n - -base zone with a life expectancy of charge carriers that is longer than 10 μsec.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-04-09 | 1999-10-09 | 2000-04-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-04-09 | 2003-10-09 | 2004-04-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-04-09 | 2007-10-09 | 2008-04-09 | $7700.00 | Window Closed / Lapsed |