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US5360983A Expired / Lapsed US ⏱️ 0.0 years remaining

Insulated gate bipolar transistor having a specific buffer layer resistance

Assignee: Fuji Electric Co Ltd
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Filing: 1993-04-16
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Granted: 1994-11-01
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Expires: 2013-04-16
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Abstract

Abstract An n + buffer layer, that is located between an n - base layer and a p + substrate, has a resistivity in the range of 0.005-0.03 Ωcm and a thickness not more than 10μm. Further, the base layer has an impurity concentration not more than (0.3×I 1 )/(S×1.6×10 -19 ×6.0×10 6 ), where I 1 is a rated current in ampere and S is an effective are in cm 2 .

Inventors

  • 👤 Noriyuki Iwamuro

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-07 16:15
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/141; H10D62/142; H10D12/00; H10D12/411; H10D12/441

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 180 words
An insulated gate bipolar transistor comprising in a semiconductor base: a first region of a first conduction type; a second region of a second conduction type formed on the first region; a third region of the second conduction type formed on the second region and having a low impurity concentration; a fourth region of the first conduction type selectively formed in a surface layer of the third region; and a fifth region of the second conduction type selectively formed in a surface layer of the fourth region and having a high impurity concentration; said insulated gate bipolar transistor further comprising: a gate electrode formed, via a gate insulating film, on a surface portion of the fourth region which portion is interposed between the third and fifth regions and serves as a channel region; a source electrode being commonly in contact with the fourth and fifth regions; and a drain electrode being in contact with the first region; wherein the second region has a resistivity in a range of 0.005 to 0.03 Ωcm and a thickness not more than 10 μm.
Claim 2
Dependent Claim 180 words
An insulated gate bipolar transistor comprising in a semiconductor base: a first region of a first conduction type; a second region of a second conduction type formed on the first region; a third region of the second conduction type formed on the second region and having a low impurity concentration; a fourth region of the first conduction type selectively formed in a surface layer of the third region; and a fifth region of the second conduction type selectively formed in a surface layer of the fourth region and having a high impurity concentration; said insulated gate bipolar transistor further comprising: a gate electrode formed, via a gate insulating film, on a surface portion of the fourth region which portion is interposed between the third and fifth regions and serves as a channel region; a source electrode being commonly in contact with the fourth and fifth regions; and a drain electrode being in contact with the first region; wherein the second region has a resistivity in a range of 0.005 to 0.03 Ωcm and a thickness not more than 10 μm.
Claim 3
Dependent Claim 39 words
The insulated gate bipolar transistor of claim 1, wherein the impurity concentration of the third region is not more than 30% of a concentration of minority carriers flowing through a depletion layer of the third region at a turn-off.
Claim 4
Dependent Claim 49 words
The insulated gate bipolar transistor of claim 2, wherein the impurity concentration of the third region is not more than (0.3×I 1 )/(S×1.6×10 -19 ×6.0×10 6 ), where I 1 is a rated current in ampere and S is an effective area in cm 2 of the semiconductor base.

References Cited (Backward Citations)

US5124772A Cited
US5237183A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-10-31 1998-05-02 1998-11-01 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-10-31 2002-05-02 2002-11-01 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-10-31 2006-05-02 2006-11-01 $7700.00 Window Closed / Lapsed

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