Patent US5504927A successfully refreshed from Google Patents.
US5504927A
Expired / Lapsed
US
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System for controlling input/output data for an integrated one-chip microcomputer utilizing an external clock of a different speed for data transfer
Assignee: Panasonic Holdings Corp
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Filing: 1992-12-21
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Granted: 1996-04-02
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Expires: 2012-12-21
Abstract
Abstract The present invention provides a data input/output control device integrating a one-chip microcomputer together with a data transfer device and a processor, the data transfer device being constructed to transmit to and receive from an external apparatus serial data and the processor processing data inputted to the data transfer device and transmitting the processed data to the data transfer device to be further transmitted to the external apparatus, the date input/output control device characterized in that a clock of the data input/output control device for an operation thereof is a transfer clock utilized by the external apparatus and the transfer clock is slower than a clock for the processor. The data input/output control device comprises a controller for controlling the data input and the data output of the data transfer device, a flag holding unit for holding a flag which shows if the data have been inputted to the data transfer device by the processor or the external apparatus, a first synchronization circuit for synchronizing an output from the flag holding unit with the transfer clock, the output being sent to the controller, and a second synchronization circuit for synchronizing the output from the flag holding unit with the clock for the processor.
Inventors
- 👤 Minoru Okamoto
- 👤 Mikio Sakakibara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:07
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4221; G06F13/423; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
229 words
A data input/output control device integrating a one-chip microcomputer together with a data transfer device and a processor, the data transfer device being constructed to transmit and receive serial data from an external apparatus the processor receiving data from the data transfer device and transmitting processed data to the data transfer device, which transmits to the external apparatus, the data input/output control device comprising: a controller for controlling data input and output of said data transfer device, said controller being supplied with a transfer clock by said external device for use as the clock for said controller, the transfer clock being slower than the clock for said processor; a flag holding circuit for holding a flag that indicates whether data has been supplied to said data transfer device by either said processor or said external apparatus; a first synchronization circuit for synchronizing the flag output from said flag holding circuit with the transfer clock, the output from said first synchronization circuit being supplied to said controller; and a second synchronization circuit for synchronizing the flag output from said flag holding circuit with the processor clock, the output from said second synchronization circuit being supplied to said processor, wherein the flag holding circuit is set by either said processor or said controller and is reset by said processor or said controller, whichever one did not set the flag holding circuit.
Claim 2
Dependent Claim
229 words
A data input/output control device integrating a one-chip microcomputer together with a data transfer device and a processor, the data transfer device being constructed to transmit and receive serial data from an external apparatus the processor receiving data from the data transfer device and transmitting processed data to the data transfer device, which transmits to the external apparatus, the data input/output control device comprising: a controller for controlling data input and output of said data transfer device, said controller being supplied with a transfer clock by said external device for use as the clock for said controller, the transfer clock being slower than the clock for said processor; a flag holding circuit for holding a flag that indicates whether data has been supplied to said data transfer device by either said processor or said external apparatus; a first synchronization circuit for synchronizing the flag output from said flag holding circuit with the transfer clock, the output from said first synchronization circuit being supplied to said controller; and a second synchronization circuit for synchronizing the flag output from said flag holding circuit with the processor clock, the output from said second synchronization circuit being supplied to said processor, wherein the flag holding circuit is set by either said processor or said controller and is reset by said processor or said controller, whichever one did not set the flag holding circuit.
Claim 3
Dependent Claim
124 words
The data input/output control device of claim 1, wherein said data transfer device comprises: a shift register for converting parallel transmission data from said processor into a serial data bit stream for said external apparatus, and converting serial reception data from said external apparatus into parallel data for said processor; a reception buffer for temporarily holding the data supplied to said shift register before it is supplied to said processor; a transmission buffer for temporarily holding the data supplied by said processor before it is supplied to the shift register, wherein said flag holding circuit holds a flag which shows if the transmission buffer holds data when data is to be transmitted, or the reception buffer holds data when data is to be received.
Claim 4
Dependent Claim
129 words
The data input/output control device of claim 2, wherein said controller controls said shift register transmitting and receiving serial data from said external apparatus, said controller further comprising: at the transmission of data, transferring the data in said transmission buffer to said shift register by supplying a shift clock to said shift register so that the serial data is transmitted if the flag in said flag holding circuit shows that said transmission buffer holds data; and at the reception of data, supplying a shift clock to said shift register in order to receive serial data from said external apparatus, transferring the data in said shift register to said reception buffer, and changing the flag in said flag holding circuit to show that reception data is in said reception buffer.
Claim 5
Dependent Claim
126 words
The data input/output control device of claim 3, wherein said controller comprises: a transmission control circuit for generating a load signal to load said shift register with the transmission data when the flag from said flag holding circuit shows that the transmission buffer holds data; a shift clock output circuit for generating a shift clock for the shift register when the shift register is loaded with the transmission data and when a transfer ready signal is supplied to said external apparatus indicating the reception of the data from said external apparatus; and a reception control circuit for obtaining an indication that reception of data the shift register is complete and changing the flag in said flag holding circuit to show that reception data is held therein.
Claim 6
Dependent Claim
46 words
The data input/output control device of claim 4 further comprising a counter for counting the number of bits in the serial data stream to be transferred when the serial data is transferred to the external apparatus, when the serial data is transferred from the external apparatus.
Claim 7
Dependent Claim
223 words
An improved one-chip microcomputer comprising a data transfer device for transmitting serial data to and receiving serial data from an external apparatus, a data input/output control device for controlling said data transfer device, and a processor for receiving data from and transmitting data to said external apparatus via said data transfer device, the improvement therein comprising: a controller for controlling data input and output of said data transfer device, said controller being supplied with a transfer clock by said external device for use as the clock for said controller, the transfer clock being slower than the clock for said processor; a flag holding circuit for holding a flag that indicates whether data has been supplied to said data transfer device by either said processor or said external apparatus; a first synchronization circuit for synchronizing the flag output from said flag holding circuit with the transfer clock, the output from said first synchronization circuit being supplied to said controller; and a second synchronization circuit for synchronizing the flag output from said flag holding circuit with the processor clock, the output from said second synchronization circuit being supplied to said processor, wherein the flag holding circuit is set by either said processor or said controller and is reset by said processor or said controller, whichever one previously did not set the said flag holding circuit.
Claim 8
Dependent Claim
223 words
An improved one-chip microcomputer comprising a data transfer device for transmitting serial data to and receiving serial data from an external apparatus, a data input/output control device for controlling said data transfer device, and a processor for receiving data from and transmitting data to said external apparatus via said data transfer device, the improvement therein comprising: a controller for controlling data input and output of said data transfer device, said controller being supplied with a transfer clock by said external device for use as the clock for said controller, the transfer clock being slower than the clock for said processor; a flag holding circuit for holding a flag that indicates whether data has been supplied to said data transfer device by either said processor or said external apparatus; a first synchronization circuit for synchronizing the flag output from said flag holding circuit with the transfer clock, the output from said first synchronization circuit being supplied to said controller; and a second synchronization circuit for synchronizing the flag output from said flag holding circuit with the processor clock, the output from said second synchronization circuit being supplied to said processor, wherein the flag holding circuit is set by either said processor or said controller and is reset by said processor or said controller, whichever one previously did not set the said flag holding circuit.
Claim 9
Dependent Claim
124 words
The data input/output control device of claim 6, wherein said data transfer device comprises: a shift register for converting parallel transmission data from said processor into a serial data bit stream for said external apparatus, and converting serial reception data from said external apparatus into parallel data for said processor; a reception buffer for temporarily holding the data supplied to said shift register before it is supplied to said processor; a transmission buffer for temporarily holding the data supplied by said processor before it is supplied to the shift register, wherein said flag holding circuit holds a flag which shows if the transmission buffer holds data when data is to be transmitted, or the reception buffer holds data when data is to be received.
Claim 10
Dependent Claim
134 words
The data input/output control device of claim 7, wherein said controller controls said shift register transmitting and receiving serial data from said external apparatus, and, said controller further comprising: at the transmission of data, transferring the data in said transmission buffer to said shift register by supplying a shift clock to said shift register so that the serial data is transmitted if said flag in said flag holding circuit shows that said transmission buffer holds data; and at the reception of data, supplying a shift clock to said shift register so that the serial data from said external apparatus is received, the reception data in said shift register is transferred to said reception buffer, and the flag in said flag holding circuit is changed to show that reception data is in said reception buffer.
Claim 11
Dependent Claim
134 words
The data input/output control device of claim 8, wherein said controller comprises: a transmission control circuit for generating a load signal to load said shift register with transmission data when said flag from the flag holding circuit shows that the transmission buffer holds data; a shift clock output circuit for generating a shift clock for the shift register when the shift register is loaded with transmission data, as well as outputting the shift clock to the shift register when a transfer ready signal is supplied to said external apparatus indicating the reception of the data from said external apparatus; and a reception control circuit for obtaining an indication that reception of data the shift register is complete and changing the flag in said flag holding circuit to show that reception data is held therein.
Claim 12
Dependent Claim
45 words
The data input/output control device of claim 9 further comprising a counter for counting the number of bits in the serial bit data stream when the serial data is transferred to the external apparatus, and when the serial data is transferred from the external apparatus.
References Cited (Backward Citations)
US4435761A
Cited
US4473879A
Cited
US4841440A
Cited
US4642791A
Cited
JPS60107168A
Cited
EP0258872A2
Cited
US4761735A
Cited
US5200925A
Cited
JPH0381851A
Cited
JPH03228161A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-04-02 | 1999-10-02 | 2000-04-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-04-02 | 2003-10-02 | 2004-04-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-04-02 | 2007-10-02 | 2008-04-02 | $7700.00 | Window Closed / Lapsed |