US4435761A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data processing apparatus capable of transferring serial data with small power consumption
Assignee: NEC Corp
•
Filing: 1980-10-07
•
Granted: 1984-03-06
•
Expires: 2000-10-07
Abstract
Abstract In a data processing apparatus comprising a data transmitting and receiving unit for transferring data and a processing unit for processing the data, means is provided for stopping supply of a control clock signal to circuit elements which are in an inoperative state.
Inventors
- 👤 Manabu Kimoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 17:52
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3234; G06F1/3287; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4221; G06F13/423; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
188 words
Data processing apparatus comprising: a central processing unit having an arithmetic operation circuit and an output circuit for producing a data transfer initiation signal for designating a start of data transfer, transfer means coupled to said central processing unit for transferring data from said central processing unit to a receiving unit, a clock pulse generator for generating a clock pulse controlling the arithmetic operation of said central processing unit and said data transfer operation of said transfer means, control means coupled to said central processing unit, said transfer means and said clock pulse generator for sending said clock pulse to said transfer means in response to said initiation signal, means for sending said clock pulse from said clock pulse generator to said central processing unit, inhibiting means coupled to said sending means for inhibiting the sending of said clock pulse to said central processing unit when said transfer means is operating to transfer said data according to said clock pulse, and releasing means coupled to said control means for releasing the inhibitation of the sending of said clock pulse to said central processing unit upon data transfer termination.
Claim 2
Dependent Claim
188 words
Data processing apparatus comprising: a central processing unit having an arithmetic operation circuit and an output circuit for producing a data transfer initiation signal for designating a start of data transfer, transfer means coupled to said central processing unit for transferring data from said central processing unit to a receiving unit, a clock pulse generator for generating a clock pulse controlling the arithmetic operation of said central processing unit and said data transfer operation of said transfer means, control means coupled to said central processing unit, said transfer means and said clock pulse generator for sending said clock pulse to said transfer means in response to said initiation signal, means for sending said clock pulse from said clock pulse generator to said central processing unit, inhibiting means coupled to said sending means for inhibiting the sending of said clock pulse to said central processing unit when said transfer means is operating to transfer said data according to said clock pulse, and releasing means coupled to said control means for releasing the inhibitation of the sending of said clock pulse to said central processing unit upon data transfer termination.
Claim 3
Dependent Claim
32 words
The data processing apparatus according to claim 1, wherein said clock pulse generated by said clock pulse generator is sent to said transfer means and said central processing unit through different paths.
Claim 4
Dependent Claim
29 words
The data processing apparatus according to claim 2, further comprising, indicating means for indicating termination of the data transfer, wherein said releasing means is activated by said indicating means.
Claim 5
Dependent Claim
163 words
Data processing apparatus comprising: a data processing means which executes a programmed process and generates a data transfer initiating signal and a signal for halting execution of said programmed process, a data transfer means coupled to said data processing means for transferring data processed by said data processing means to a receiving unit, a clock pulse generator for generating a clock pulse, means for sending said clock pulse to said data processing means, a first control means coupled to said sending means for inhibiting the sending of said clock pulse to said data processing means in response to said signal for halting execution, a second control means coupled to said data transfer means and said clock pulse generator for sending said clock pulse to said data transfer means in response to said data transfer initiating signal, and a third control means coupled to said first control means for sending said clock pulse to said data processing means in response to data transfer termination.
Claim 6
Dependent Claim
163 words
Data processing apparatus comprising: a data processing means which executes a programmed process and generates a data transfer initiating signal and a signal for halting execution of said programmed process, a data transfer means coupled to said data processing means for transferring data processed by said data processing means to a receiving unit, a clock pulse generator for generating a clock pulse, means for sending said clock pulse to said data processing means, a first control means coupled to said sending means for inhibiting the sending of said clock pulse to said data processing means in response to said signal for halting execution, a second control means coupled to said data transfer means and said clock pulse generator for sending said clock pulse to said data transfer means in response to said data transfer initiating signal, and a third control means coupled to said first control means for sending said clock pulse to said data processing means in response to data transfer termination.
Claim 7
Dependent Claim
31 words
The data processing apparatus according to claim 4, wherein said data processing means and said data transfer means are controlled by the same clock pulse so as to operate in synchronism.
Claim 8
Dependent Claim
45 words
The data processing apparatus according to claim 4, wherein data from said data processing means are comprised of a plurality of digital bits which are transferred in parallel to said data transfer means, and said data transfer means serially transfers said plurality of parallel bits.
Claim 9
Dependent Claim
181 words
Data processing apparatus comprising: a central processing unit for processing data, a shift register which simultaneously receives said data, each unit of data consisting of a plurality of bits from said central processing unit, and serially transfers said bits to a receiving unit, means for generating a clock pulse that controls the processing operation of said central processing unit and shift operation of said shift register, means for generating a signal to initiate transfer of said data by said shift register, a counter for counting a transfer period according to said clock pulse, means for sending said clock pulse to said shift register while said counter is counting during said transfer period, means for sending said clock pulse to said central processing unit, means for inhibiting the sending of said clock pulse to said central processing unit while said clock pulse is being sent to said shift register, and means for controlling said inhibiting means according to an output of said counter means so as to send said clock pulse to said central processing unit in synchronism with data transfer termination.
Claim 10
Dependent Claim
181 words
Data processing apparatus comprising: a central processing unit for processing data, a shift register which simultaneously receives said data, each unit of data consisting of a plurality of bits from said central processing unit, and serially transfers said bits to a receiving unit, means for generating a clock pulse that controls the processing operation of said central processing unit and shift operation of said shift register, means for generating a signal to initiate transfer of said data by said shift register, a counter for counting a transfer period according to said clock pulse, means for sending said clock pulse to said shift register while said counter is counting during said transfer period, means for sending said clock pulse to said central processing unit, means for inhibiting the sending of said clock pulse to said central processing unit while said clock pulse is being sent to said shift register, and means for controlling said inhibiting means according to an output of said counter means so as to send said clock pulse to said central processing unit in synchronism with data transfer termination.
Claim 11
Dependent Claim
189 words
Data processing apparatus formed on a semiconductor chip comprising: a central processing circuit for arithmetically processing data according to at least one instruction, a data transfer circuit coupled to said central processing circuit and at least one terminal for transferring a processed unit of data to said terminal, a clock pulse input circuit for receiving a clock pulse, a first supply circuit coupled to said clock pulse input circuit for supplying the received clock pulse to said central processing circuit, a second supply circuit coupled to said clock pulse input circuit for supplying said clock pulse to said data transfer circuit, said first supply circuit and said second supply circuit being formed on said semiconductor chip, a first control circuit coupled to said second supply circuit for controlling said second supply circuit so as to send said clock pulse to said data transfer circuit when said processed unit of data is being transferred by said data transfer circuit, and a second control circuit for controlling said first supply circuit to stop sending said clock pulse to said central processing circuit during at least a part of said data transfer.
Claim 12
Dependent Claim
189 words
Data processing apparatus formed on a semiconductor chip comprising: a central processing circuit for arithmetically processing data according to at least one instruction, a data transfer circuit coupled to said central processing circuit and at least one terminal for transferring a processed unit of data to said terminal, a clock pulse input circuit for receiving a clock pulse, a first supply circuit coupled to said clock pulse input circuit for supplying the received clock pulse to said central processing circuit, a second supply circuit coupled to said clock pulse input circuit for supplying said clock pulse to said data transfer circuit, said first supply circuit and said second supply circuit being formed on said semiconductor chip, a first control circuit coupled to said second supply circuit for controlling said second supply circuit so as to send said clock pulse to said data transfer circuit when said processed unit of data is being transferred by said data transfer circuit, and a second control circuit for controlling said first supply circuit to stop sending said clock pulse to said central processing circuit during at least a part of said data transfer.
Claim 13
Dependent Claim
34 words
The data processing apparatus according to claim 8, further comprising on said semiconductor chip at least one control signal output terminal and means for transferring said clock pulse to said control signal output terminal.
Claim 14
Dependent Claim
107 words
Data processing apparatus comprising: a central processing unit for executing an arithmetic logic operation according to a predetermined program, a data transfer unit coupled to said central processing unit for transferring data which is obtained by said central processing unit to a receiving unit, a clock signal supply unit coupled to said central processing unit and said data transfer unit for supplying a clock signal to said central processing unit and said data transfer unit, respectively, and a control unit coupled to said clock signal supply unit for controlling said clock signal supply unit so as to inhibit sending said clock signal to said central processing unit.
Claim 15
Dependent Claim
107 words
Data processing apparatus comprising: a central processing unit for executing an arithmetic logic operation according to a predetermined program, a data transfer unit coupled to said central processing unit for transferring data which is obtained by said central processing unit to a receiving unit, a clock signal supply unit coupled to said central processing unit and said data transfer unit for supplying a clock signal to said central processing unit and said data transfer unit, respectively, and a control unit coupled to said clock signal supply unit for controlling said clock signal supply unit so as to inhibit sending said clock signal to said central processing unit.
References Cited (Backward Citations)
US4137563A
Cited
US4203153A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-03-06 | 1987-09-05 | 1988-03-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-03-06 | 1991-09-05 | 1992-03-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-03-06 | 1995-09-05 | 1996-03-06 | $7700.00 | Window Closed / Lapsed |