EP0258872A2
Expired / Lapsed
EP
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Serial data transfer system
Assignee: NEC Corp
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Filing: 1987-09-01
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Granted: —
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Expires: 2007-09-01
Abstract
Abstract Herein disclosed is a serial data transfer system which has first and second serial data processors connected via a single data line and a single clock line for transferring serial data therebetween. Each of the first and second serial data processors includes: reception confirmation signal output means for outputting a reception confirmation signal to the data line; and reception confirmation signal detection means for detecting the reception confirmation signal on the data line. The confirmation of the data transfer is executed in synchronism with serial clock pulses outputted to the clock line. Alternatively, the first or second serial data processor includes: an output circuit for outputting a reception confirmation signal to the data line; a circuit for generating a first signal indicating the end of reception of the serial data; a circuit for generating a second signal indicating the end of processing of the data received; and a circuit for controlling the output of said reception confirmation signal. When the reception of the serial data on the data line is ended, the output circuit outputs the reception confirmation signal to the data line in synchronism with the first or second signal.
Inventors
- 👤 Shigetatsu C/O Nec Corporation Katori
- 👤 Yukio C/O Nec Corporation Maehashi
- 👤 Yukari C/O Nec Corporation Misawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 12:45
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4221; G06F13/423; G06F13/14; G06F13/20; G06F13/28; G06F15/00; G06F15/16; G06F15/163; G06F15/17
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
132 words
A serial data transfer system comprising: a first serial data processor acting as a master; a second serial data processor acting as a slave; a data line connecting said first and second serial data processors for allowing serial data to be transferred therethrough between said first and second serial data processors; and a clock line connecting said first and second serial data processors, wherein the improvement resides: in that each of said first and second serial data processors includes: reception confirmation signal output means for outputting a reception confirmation signal to said data line; and reception confirmation signal detection means for detecting said reception confirmation signal on said data line; and in that the confirmation of the data transfer is executed in synchronism with serial clock pulses outputted to said clock line.
Claim 2
Dependent Claim
132 words
A serial data transfer system comprising: a first serial data processor acting as a master; a second serial data processor acting as a slave; a data line connecting said first and second serial data processors for allowing serial data to be transferred therethrough between said first and second serial data processors; and a clock line connecting said first and second serial data processors, wherein the improvement resides: in that each of said first and second serial data processors includes: reception confirmation signal output means for outputting a reception confirmation signal to said data line; and reception confirmation signal detection means for detecting said reception confirmation signal on said data line; and in that the confirmation of the data transfer is executed in synchronism with serial clock pulses outputted to said clock line.
Claim 3
Dependent Claim
26 words
A serial data transfer system according to Claim 1, wherein said reception confirmation signal detection means detects said reception confirmation signal for a predetermined sampling period.
Claim 4
Dependent Claim
112 words
A serial data transfer system according to Claim 1, wherein each of said first and second serial data processors further includes: a shift register; a serial clock generator for generating said serial clock pulses; a serial clock source flag for changing one of said first and second serial data processors, to which it belongs, into said master when set and into said slave when reset; a data processing unit for reading and writing the sent and received data from and in said shift register and for setting and resetting said serial clock source flag; and an internal bus connecting said shift register, said data processing unit and said serial clock source flag.
Claim 5
Dependent Claim
107 words
A serial data transfer system according to Claim 3, wherein each of said first and second serial data processors further includes a serial clock control for outputting a reception confirmation signal sampling signal for designating said sampling period to said reception confirmation signal detection means, wherein said reception confirmation signal output means includes a reception confirmation signal trigger flag for outputting said reception confirmation signal when controlled by said data processing unit, and wherein said reception confirmation signal detection means includes a reception confirmation signal detection flag adapted to be set, if said reception confirmation signal is confirmed to have been outputted to said serial data line.
Claim 6
Dependent Claim
162 words
A serial data transfer system comprising: first and second serial data processors; a data line connecting said first and second serial data processors for allowing serial data to be transferred therethrough between said first and second serial data processors; and a clock line connecting said first and second serial data processors, wherein the improvement resides: in that each of said first and second serial data processors includes: an output circuit for outputting a reception confirmation signal to said data line; a circuit for generating a first signal indicating the end of reception of said serial data; a circuit for generating a second signal indicating the end of processing of the data received; and a circuit for controlling the output of said reception confirmation signal; and in that, when the reception of the serial data on said data line is ended, said output circuit outputs said reception confirmation signal to said data line in synchronism with said first signal or said second signal.
Claim 7
Dependent Claim
162 words
A serial data transfer system comprising: first and second serial data processors; a data line connecting said first and second serial data processors for allowing serial data to be transferred therethrough between said first and second serial data processors; and a clock line connecting said first and second serial data processors, wherein the improvement resides: in that each of said first and second serial data processors includes: an output circuit for outputting a reception confirmation signal to said data line; a circuit for generating a first signal indicating the end of reception of said serial data; a circuit for generating a second signal indicating the end of processing of the data received; and a circuit for controlling the output of said reception confirmation signal; and in that, when the reception of the serial data on said data line is ended, said output circuit outputs said reception confirmation signal to said data line in synchronism with said first signal or said second signal.
Claim 8
Dependent Claim
111 words
A serial data transfer system according to Claim 5, wherein each of said first and second serial data processors further includes: a shift register; a serial clock generator for generating serial clock pulses; a serial clock source flag for changing one of said first and second serial data processors, to which it belongs, into a master when set and into a slave when reset; a data processing unit for reading and writing the sent and received data from and in said shift register and for setting and resetting said serial clock source flag; and an internal bus connecting said shift register, said data processing unit and said serial clock source flag.
Claim 9
Dependent Claim
73 words
A serial data transfer system according to Claim 6, wherein each of said first and second serial data processors further includes a serial clock control for outputting a reception confirmation signal sampling signal for designating a sampling period of said reception confirmation signal to said output circuit, and wherein said output circuit includes a reception confirmation signal output selection flag for synchronizing said output circuit with said first signal or said second signal.
Claim 10
Dependent Claim
53 words
A serial data transfer system according to Claim 7, wherein said output circuit further includes a serial clock counter having: a count register controlled by said data processing unit for storing timing information; and a subtracter for decrementing said timing information in synchronism with the start of generation of said serial clock pulses.
References Cited (Backward Citations)
No citation records indexed.
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