Serial access semiconductor memory device and operating method therefor

Claim 2

A serial access semiconductor memory device, comprising: a memory cell array divided into a plurality of blocks, a plurality of register means each provided corresponding to each said plurality of blocks for receiving and sending data from and to memory cells on a selected row in the corresponding block, each of said plurality of register means including means for data latching and shifting data, a plurality of input buffer means each provided separately corresponding to each said plurality of register means for serially transmitting externally applied data to the corresponding register, said plurality of input buffer means receiving different data from each other in a sequential data stream, a plurality of output buffer means each provided corresponding to each of said plurality of register means for serially outputting the data received from the corresponding register means, wherein timing of the activation of the input buffer means and the output buffer means for each of the memory cell array blocks is different, means for providing an external clock signal and a write/read enabling signal; and logic means responsive to said external clock signal and said write/read enabling signal for generating an internal clock signal; wherein said internal clock signal is applied in common to said plurality of register means, so that a shifting operation in each of said plurality of register means is performed in response to the same internal clock signal, and the relationship of operation timing between said plurality of register means and said plurality of input buffer means during a data writing operation differs from the relationship of operation timing between said plurality of register means and said plurality of output buffer means during a data reading operation.

Claim 3

A device in accordance with claim 1, wherein said internal clock signal generating means include means for providing a write clock signal having a first activating timing for the data write operation and providing a read clock signal having a second activating timing, different from said first activating timing, for the data reading operation.

Claim 4

A device in accordance with claim 1, wherein said internal clock signal generating means include means for providing a clock signal as said internal clock signal in synchronization with operation of a first activated output buffer means among said plurality of output buffer means in the data reading operation.

Claim 5

A device in accordance with claim 1, wherein said internal clock generating means include means for providing a clock signal as said internal clock signal in synchronization with operation of one input buffer means among said plurality of input means in the data writing operation.

Claim 6

A serial access memory device, comprising: a first memory cell array having a plurality of memory cells, a first shift register for latching and shifting a series of read-out data in reading out the series of read-out data from a series of memory cells of said first memory cell array and for latching and shifting a series of written-in data in writing the series of written-in data into a series of memory cells of said first memory cell array; a first output buffer connected to an output node of said first shift register for providing the read-out data latched in said first register to an output node of said memory device, based on a first clock signal; a first input buffer receiving incoming data for providing selectively data to be written into the series of memory cells of said first memory cell array among said incoming data, based on a second clock signal; a second memory cell array having a plurality of memory cells, a second shift register for latching and shifting a series of read-out data in reading out the series of read-out data out of a series of memory cells of said second memory cell array and for latching and shifting a series of written-in data in writing the series of written-in data into a series of memory cells of said second memory cell array; a second output buffer connected to said second shift register for providing the read-out data latched in said second shift register to said output node of said memory device, based on a third clock signal delayed in the phase to said first clock signal; a second input buffer receiving the incoming data for providing selectively among the incoming data the data to be written into a series of memory cells of said second memory cell array to said second shift register, based on a fourth clock signal delayed in the phase to said second clock signal; means for generating a first control signal in phase with said first clock signal, for controlling the shifting of data latched in said first and second shift registers in reading out the data of the series of memory cells of said first memory cell array latched in said first shift register and the data of the series of memory cells of said second memory cell array latched in said second shift register; and means for generating a second control signal for controlling the respective shiftings of data from said first and second input buffers to said first and second shift registers, said second control signal being in phase with said fourth clock signal; wherein the relationship of operation timing between said registers and said input buffers differs from the relationship of operation timing between said registers said output buffers.

Claim 7

A serial access memory device, comprising: a first memory cell array having a plurality of memory cells, a first shift register for latching and shifting a series of read-out data in reading out the series of read-out data from a series of memory cells of said first memory cell array and for latching and shifting a series of written-in data in writing the series of written-in data into a series of memory cells of said first memory cell array; a first output buffer connected to an output node of said first shift register for providing the read-out data latched in said first register to an output node of said memory device, based on a first clock signal; a first input buffer receiving incoming data for providing selectively data to be written into the series of memory cells of said first memory cell array among said incoming data, based on a second clock signal; a second memory cell array having a plurality of memory cells, a second shift register for latching and shifting a series of read-out data in reading out the series of read-out data out of a series of memory cells of said second memory cell array and for latching and shifting a series of written-in data in writing the series of written-in data into a series of memory cells of said second memory cell array; a second output buffer connected to said second shift register for providing the read-out data latched in said second shift register to said output node of said memory device, based on a third clock signal delayed in the phase to said first clock signal; a second input buffer receiving the incoming data for providing selectively among the incoming data the data to be written into a series of memory cells of said second memory cell array to said second shift register, based on a fourth clock signal delayed in the phase to said second clock signal; means for generating a first control signal in phase with said first clock signal, for controlling the shifting of data latched in said first and second shift registers in reading out the data of the series of memory cells of said first memory cell array latched in said first shift register and the data of the series of memory cells of said second memory cell array latched in said second shift register; and means for generating a second control signal for controlling the respective shiftings of data from said first and second input buffers to said first and second shift registers, said second control signal being in phase with said fourth clock signal; wherein the relationship of operation timing between said registers and said input buffers differs from the relationship of operation timing between said registers said output buffers.

Claim 10

A method according to claim 6, wherein said internal clock signal generating step includes providing clock signals different in activating timing for the data write operation and the data reading operation.

Claim 11

A method according to claim 6, wherein said internal clock signal generating step includes providing a clock signal as said internal clock signal in synchronization with operation of a first activated output buffer means among said plurality of output buffer means in the data reading operation.

Claim 12

A method according to claim 6, wherein said internal clock generating step includes providing a clock signal as said internal clock signal in synchronization with operation of one input buffer means among said plurality of input means in the data writing operation.

Claim 13

A video random access memory device (VRAM) for reading and writing pixel data, comprising: a memory cell array divided into a plurality of blocks, a plurality of register means each provided corresponding to each said plurality of blocks for receiving and sending data from and to memory cells on a selected row in the corresponding block, each of said plurality of register means including means for data latching and shifting data, a plurality of input buffer means each provided separately corresponding to each said plurality of register means for serially transmitting externally applied data to the corresponding register, said plurality of input buffer means receiving different data from each other in a sequential data stream, a plurality of output buffer means each provided corresponding to each of said plurality of register means for serially outputting the data received from the corresponding register means, wherein timing of the activation of the input buffer means and the output buffer means for each of the memory cell array blocks is different, means for dividing down a chrominance subcarrier; and means responsive to said divided down chrominance subcarrier and a write/read enabling signal for deriving an internal clock signal; wherein said internal clock signal is applied in common to said plurality of register means, so that a shifting operation in each of said plurality of register means is performed in responsive to the same internal clock signal, and the relationship of operation timing between said plurality of register means and said plurality of input buffer means during a data writing operation differs from the relationship of operation timing between said plurality of register means and said plurality of output buffer means during a data reading operation.

Claim 14

A video random access memory device (VRAM) for reading and writing pixel data, comprising: a memory cell array divided into a plurality of blocks, a plurality of register means each provided corresponding to each said plurality of blocks for receiving and sending data from and to memory cells on a selected row in the corresponding block, each of said plurality of register means including means for data latching and shifting data, a plurality of input buffer means each provided separately corresponding to each said plurality of register means for serially transmitting externally applied data to the corresponding register, said plurality of input buffer means receiving different data from each other in a sequential data stream, a plurality of output buffer means each provided corresponding to each of said plurality of register means for serially outputting the data received from the corresponding register means, wherein timing of the activation of the input buffer means and the output buffer means for each of the memory cell array blocks is different, means for dividing down a chrominance subcarrier; and means responsive to said divided down chrominance subcarrier and a write/read enabling signal for deriving an internal clock signal; wherein said internal clock signal is applied in common to said plurality of register means, so that a shifting operation in each of said plurality of register means is performed in responsive to the same internal clock signal, and the relationship of operation timing between said plurality of register means and said plurality of input buffer means during a data writing operation differs from the relationship of operation timing between said plurality of register means and said plurality of output buffer means during a data reading operation.

Claim 15

A VRAM in accordance with claim 10, wherein said internal clock signal deriving means include means for providing a write clock signal having a first activating timing for the data writing operation and providing a read clock signal having a second activating timing, different from said first activating timing, for the data reading operation.

Claim 16

A VRAM in accordance with claim 10, wherein said internal clock signal deriving means include means for providing a clock signal in synchronization with operation of a first activated output buffer means among said plurality of output buffer means in the data reading operation.

Claim 17

A VRAM in accordance with claim 10, wherein said internal clock deriving means include means for providing a clock signal as said internal clock signal in synchronization with operation of one input buffer means among said plurality of input means in the data writing operation.

Claim 18

A video random access memory comprising: a first memory cell array having a plurality of memory cells, a first shift register for latching and shifting a series of read-out data in reading out the series of read-out data from a series of memory cells of said first memory cell array and for latching and shifting a series of written-in data in writing the series of written-in data into a series of memory cells of said first memory cell array; a first output buffer connected to an output node of said first shift register for providing the read-out data latched in said first register to an output node of said memory device, based on a first clock signal; a first input buffer receiving incoming data for providing selectively data to be written into the series of memory cells of said first memory cell array among said incoming data, based on a second clock signal; a second memory cell array having a plurality of memory cells, a second shift register for latching and shifting a series of read-out data in reading out the series of read-out data out of a series of memory cells of said second memory cell array and for latching and shifting a series of written-in data in writing the series of written-in data into a series of memory cells of said second memory cell array; a second output buffer connected to said second shift register for providing the read-out data latched in said second shift register to said output node of said memory device, based on a third clock signal delayed in the phase to said first clock signal; a second input buffer receiving the incoming data for providing selectively among the incoming data to be written into a series of memory cells of said second memory cell array to said second shift register, based on a fourth clock signal delayed in the phase to said second clock signal; means for generating a first control signal in phase with said first clock signal, for controlling the shifting of data latched in said first and second shift registers in reading out the data of the series of memory cells of said first memory cell array latched in said first shift register and the data of the series of memory cells of said second memory cell array latched in said second shift register; means for generating a second control signal for controlling the respective shiftings of data from said first and second input buffers to said first and second shift registers, said second control signal being in phase with said fourth clock signal; and means for generating said first and second clock signals by dividing means a chrominance subcarrier externally applied; wherein the relationship of operation timing between said registers and said input buffers differs from the relationship of operation timing between said registers and said output buffers.

Claim 19

A video random access memory comprising: a first memory cell array having a plurality of memory cells, a first shift register for latching and shifting a series of read-out data in reading out the series of read-out data from a series of memory cells of said first memory cell array and for latching and shifting a series of written-in data in writing the series of written-in data into a series of memory cells of said first memory cell array; a first output buffer connected to an output node of said first shift register for providing the read-out data latched in said first register to an output node of said memory device, based on a first clock signal; a first input buffer receiving incoming data for providing selectively data to be written into the series of memory cells of said first memory cell array among said incoming data, based on a second clock signal; a second memory cell array having a plurality of memory cells, a second shift register for latching and shifting a series of read-out data in reading out the series of read-out data out of a series of memory cells of said second memory cell array and for latching and shifting a series of written-in data in writing the series of written-in data into a series of memory cells of said second memory cell array; a second output buffer connected to said second shift register for providing the read-out data latched in said second shift register to said output node of said memory device, based on a third clock signal delayed in the phase to said first clock signal; a second input buffer receiving the incoming data for providing selectively among the incoming data to be written into a series of memory cells of said second memory cell array to said second shift register, based on a fourth clock signal delayed in the phase to said second clock signal; means for generating a first control signal in phase with said first clock signal, for controlling the shifting of data latched in said first and second shift registers in reading out the data of the series of memory cells of said first memory cell array latched in said first shift register and the data of the series of memory cells of said second memory cell array latched in said second shift register; means for generating a second control signal for controlling the respective shiftings of data from said first and second input buffers to said first and second shift registers, said second control signal being in phase with said fourth clock signal; and means for generating said first and second clock signals by dividing means a chrominance subcarrier externally applied; wherein the relationship of operation timing between said registers and said input buffers differs from the relationship of operation timing between said registers and said output buffers.

Claim 22

A method in accordance with the claim 15, wherein said step of generating the internal clock signal includes the step of generating clock signals different in activating timing for the data writing operation and for the data reading operation.

Claim 23

A serial access semiconductor memory device, comprising: a memory cell array divided into a plurality of blocks, a plurality of register means each provided corresponding to each said plurality of blocks for receiving and sending data from and to memory cells on a selected row in the corresponding block, each of said plurality of register means including means for data latching and shifting data, a plurality of input buffer means each provided separately corresponding to each said plurality of register means for serially transmitting externally applied data to the corresponding register, said plurality of input buffer means receiving different data from each other in a sequential data stream, a plurality of output buffer means each provided corresponding to each of said plurality of register means for serially outputting the data received from the corresponding register means, wherein timing of the activation of the input buffer means and the output means for each of the memory cell array blocks is different, means for providing an external clock signal and a write/read enabling signal; and logic means responsive to said external clock signal and said write/read enabling signal for generating an internal clock signal, wherein said logic means include means for providing a write clock signal having a first activating timing for a data writing operation and providing a read clock signal having a second activating timing, different from said first activating timing, for a data reading operation; wherein said internal clock signal is applied in common to said plurality of register means, so that a shifting operation in each of said plurality of register means is performed in response to the same internal clock signal.

Claim 24

A serial access semiconductor memory device, comprising: a memory cell array divided into a plurality of blocks, a plurality of register means each provided corresponding to each said plurality of blocks for receiving and sending data from and to memory cells on a selected row in the corresponding block, each of said plurality of register means including means for data latching and shifting data, a plurality of input buffer means each provided separately corresponding to each said plurality of register means for serially transmitting externally applied data to the corresponding register, said plurality of input buffer means receiving different data from each other in a sequential data stream, a plurality of output buffer means each provided corresponding to each of said plurality of register means for serially outputting the data received from the corresponding register means, wherein timing of the activation of the input buffer means and the output means for each of the memory cell array blocks is different, means for providing an external clock signal and a write/read enabling signal; and logic means responsive to said external clock signal and said write/read enabling signal for generating an internal clock signal, wherein said logic means include means for providing a write clock signal having a first activating timing for a data writing operation and providing a read clock signal having a second activating timing, different from said first activating timing, for a data reading operation; wherein said internal clock signal is applied in common to said plurality of register means, so that a shifting operation in each of said plurality of register means is performed in response to the same internal clock signal.

Claim 25

A serial access semiconductor memory device, comprising: a memory cell array divided into a plurality of blocks, a plurality of register means each provided corresponding to each said plurality of blocks for receiving and sending data from and to memory cells on a selected row in the corresponding block, each of said plurality of register means including means for data latching and shifting data, a plurality of input buffer means each provided separately corresponding to each said plurality of register means for serially transmitting externally applied data to the corresponding register, said plurality of input buffer means receiving different data from each other in a sequential data stream, a plurality of output buffer means each provided corresponding to each of said plurality of register means for serially outputting the data received from the corresponding register means, wherein timing of the activation of the input buffer means and the output means for each of the memory cell array blocks is different, means for providing an external clock signal and a write/read enabling signal; and logic means responsive to said external clock signal and said write/read enabling signal for generating an internal clock signal, wherein said logic means include (i) means for providing a clock signal as said internal clock signal in synchronization with operation of a first activated output buffer means among said plurality of output buffer means in a data reading operation, and (ii) means for providing a clock signal as said internal clock signal in syncrhonization with operation of one input buffer means among said plurality of input means in a data writing operation; wherein said internal clock signal is applied in common to said plurality of register means, so that a shifting operation in each of said plurality of register means is performed in response to the same internal clock signal.

Claim 26

A serial access semiconductor memory device, comprising: a memory cell array divided into a plurality of blocks, a plurality of register means each provided corresponding to each said plurality of blocks for receiving and sending data from and to memory cells on a selected row in the corresponding block, each of said plurality of register means including means for data latching and shifting data, a plurality of input buffer means each provided separately corresponding to each said plurality of register means for serially transmitting externally applied data to the corresponding register, said plurality of input buffer means receiving different data from each other in a sequential data stream, a plurality of output buffer means each provided corresponding to each of said plurality of register means for serially outputting the data received from the corresponding register means, wherein timing of the activation of the input buffer means and the output means for each of the memory cell array blocks is different, means for providing an external clock signal and a write/read enabling signal; and logic means responsive to said external clock signal and said write/read enabling signal for generating an internal clock signal, wherein said logic means include (i) means for providing a clock signal as said internal clock signal in synchronization with operation of a first activated output buffer means among said plurality of output buffer means in a data reading operation, and (ii) means for providing a clock signal as said internal clock signal in syncrhonization with operation of one input buffer means among said plurality of input means in a data writing operation; wherein said internal clock signal is applied in common to said plurality of register means, so that a shifting operation in each of said plurality of register means is performed in response to the same internal clock signal.

Claim 27

A serial access memory device, comprising: a first memory cell array having a plurality of memory cells, a first shift registers for latching and shifting a series of read-out data in reading out the series of read-out data from a series of memory cells of said first memory cell array and for latching and shifting a series of written-in data in writing the series of written-in data into a series of memory cells of said first memory cell array; a first output buffer connected to an output node of said first shift register for providing the read-out data latched in said fist register to an output node of said memory device, based on a first clock signal; a first input buffer receiving incoming data for providing selectively data to be written into the series of memory cells of said first memory cell array among said incoming data, based on a second clock signal; a second memory cell array having a plurality of memory cells, a second shift register for latching and shifting a series of read-out data in reading out the series of read-out data out of a series of memory cells of said second memory cell array and for latching and shifting a series of written-in data in writing the series of written-in data into a series of memory cells of said second memory cell array; a second output buffer connected to said second shift register for providing the read-out data latched in said second shift register to said output node of said memory device, based on a third clock signal delayed in the phase to said first clock signal; a second input buffer receiving the incoming data for providing selectively among the incoming data the data to be written to a series of memory cells of said second memory cell array to said second shift register, based on a fourth clock signal delayed in the phase to said second clock signal; means for generating a first control signal in phase with said first clock signal, for controlling the shifting of data latched in said first and second shift registers in reading out the data of the series of memory cells of said first memory cell array latched in said first shift register and the data of the series of memory cells of said second memory cell array latched in said second shift register; and means for generating a second control signal for controlling the respective shiftings of data from said first and second input buffers to said first and second shift registers, said second control signal being in phase with said fourth clock signal, whereby activating timing for the data reading operation provided by said first control signal is different from the activating timing for the data writing operation provided by said second control signal.

Claim 28

A serial access memory device, comprising: a first memory cell array having a plurality of memory cells, a first shift registers for latching and shifting a series of read-out data in reading out the series of read-out data from a series of memory cells of said first memory cell array and for latching and shifting a series of written-in data in writing the series of written-in data into a series of memory cells of said first memory cell array; a first output buffer connected to an output node of said first shift register for providing the read-out data latched in said fist register to an output node of said memory device, based on a first clock signal; a first input buffer receiving incoming data for providing selectively data to be written into the series of memory cells of said first memory cell array among said incoming data, based on a second clock signal; a second memory cell array having a plurality of memory cells, a second shift register for latching and shifting a series of read-out data in reading out the series of read-out data out of a series of memory cells of said second memory cell array and for latching and shifting a series of written-in data in writing the series of written-in data into a series of memory cells of said second memory cell array; a second output buffer connected to said second shift register for providing the read-out data latched in said second shift register to said output node of said memory device, based on a third clock signal delayed in the phase to said first clock signal; a second input buffer receiving the incoming data for providing selectively among the incoming data the data to be written to a series of memory cells of said second memory cell array to said second shift register, based on a fourth clock signal delayed in the phase to said second clock signal; means for generating a first control signal in phase with said first clock signal, for controlling the shifting of data latched in said first and second shift registers in reading out the data of the series of memory cells of said first memory cell array latched in said first shift register and the data of the series of memory cells of said second memory cell array latched in said second shift register; and means for generating a second control signal for controlling the respective shiftings of data from said first and second input buffers to said first and second shift registers, said second control signal being in phase with said fourth clock signal, whereby activating timing for the data reading operation provided by said first control signal is different from the activating timing for the data writing operation provided by said second control signal.

Claim 29

A serial access memory device, comprising: a first memory cell array having a plurality of memory cells, a first shift register for latching and shifting a series of read-out data in reading out the series of read-out data from a series of memory cells of said first memory cell array and for latching and shifting a series of written-in data in writing the series of written-in data into a series of memory cells of said first memory cell array; a first output buffer connected to an output node of said first shift register for providing the read-out data latched in said first register to an output node of said memory device, based on a first clock signal; a first input buffer receiving incoming data for providing selectively data to be written into the series of memory cells of said first memory cell array among said incoming data, based on a second clock signal; a second memory cell array having a plurality of memory cells, a second shift register for latching and shifting a series of read-out data in reading out the series of read-out data out of a series of memory cells of said second memory cell array and for latching and shifting a series of written-in data in writing the series of written-in data into a series of memory cells of said second memory cell array; a second output buffer connected to said second shift register for providing the read-out data latched in said second shift register to said output node of said memory device, based on a third clock signal delayed in the phase to said first clock signal; a second input buffer receiving the incoming data for providing selectively among the incoming data the data to be written into a series of memory cells of said second memory cell array of said second shift register, based on a fourth clock signal delayed in the phase to said second clock signal; means for generating a first control signal in phase with said first clock signal and thereby in synchronization with operation of said first output buffer in the data reading operation, for controlling the shifting of data latched in said first and second shift registers in reading out the data of the series of memory cells of said first memory cell array latched in said first shift register and the data of the series of memory cells of said second memory cell array latched in said second shift register; and means for generating a second control signal for controlling the respective shiftings of data from said first and second input buffers to said first and second shift registers, said second control signal being in phase with said fourth clock signal and in synchronization with operation of the second input buffer in the data writing operation.

Claim 30

A serial access memory device, comprising: a first memory cell array having a plurality of memory cells, a first shift register for latching and shifting a series of read-out data in reading out the series of read-out data from a series of memory cells of said first memory cell array and for latching and shifting a series of written-in data in writing the series of written-in data into a series of memory cells of said first memory cell array; a first output buffer connected to an output node of said first shift register for providing the read-out data latched in said first register to an output node of said memory device, based on a first clock signal; a first input buffer receiving incoming data for providing selectively data to be written into the series of memory cells of said first memory cell array among said incoming data, based on a second clock signal; a second memory cell array having a plurality of memory cells, a second shift register for latching and shifting a series of read-out data in reading out the series of read-out data out of a series of memory cells of said second memory cell array and for latching and shifting a series of written-in data in writing the series of written-in data into a series of memory cells of said second memory cell array; a second output buffer connected to said second shift register for providing the read-out data latched in said second shift register to said output node of said memory device, based on a third clock signal delayed in the phase to said first clock signal; a second input buffer receiving the incoming data for providing selectively among the incoming data the data to be written into a series of memory cells of said second memory cell array of said second shift register, based on a fourth clock signal delayed in the phase to said second clock signal; means for generating a first control signal in phase with said first clock signal and thereby in synchronization with operation of said first output buffer in the data reading operation, for controlling the shifting of data latched in said first and second shift registers in reading out the data of the series of memory cells of said first memory cell array latched in said first shift register and the data of the series of memory cells of said second memory cell array latched in said second shift register; and means for generating a second control signal for controlling the respective shiftings of data from said first and second input buffers to said first and second shift registers, said second control signal being in phase with said fourth clock signal and in synchronization with operation of the second input buffer in the data writing operation.

Claim 35

A video random access memory device (VRAM) for reading and writing pixel data, comprising: a memory cell array divided into a plurality of blocks, a plurality of register means each provided corresponding to each said plurality of blocks for receiving an sending data from and to memory cells on a selected row in the corresponding block, each of said plurality of register means including means for data latching and shifting data, a plurality of input buffer means each provided separately corresponding to each said plurality of register means for serially transmitting externally applied data to the corresponding register, said plurality of input buffer means receiving different data from each other in a sequential data stream, a plurality of output buffer means each provided corresponding to each of said plurality of register mean for serially outputting the data received from the corresponding register means, wherein timing of the activation of the input buffer means and the output buffer means for each of the memory cell array blocks is different, means for dividing down a chrominance subcarrier; and means responsive to said divided down chrominance subcarrier and a write/read enabling signal for deriving an internal clock signal, wherein said internal clock signal deriving mean include means for providing a write clock signal having a first activating timing for a data writing operation and providing a read clock signal having a second activating timing, different from said first activating timing, for a data reading operation; wherein said internal clock signal is applied in common to said plurality of register means, so that a shifting operation in each of said plurality of register means is performed in response to the same internal clock signal.

Claim 36

A video random access memory device (VRAM) for reading and writing pixel data, comprising: a memory cell array divided into a plurality of blocks, a plurality of register means each provided corresponding to each said plurality of blocks for receiving an sending data from and to memory cells on a selected row in the corresponding block, each of said plurality of register means including means for data latching and shifting data, a plurality of input buffer means each provided separately corresponding to each said plurality of register means for serially transmitting externally applied data to the corresponding register, said plurality of input buffer means receiving different data from each other in a sequential data stream, a plurality of output buffer means each provided corresponding to each of said plurality of register mean for serially outputting the data received from the corresponding register means, wherein timing of the activation of the input buffer means and the output buffer means for each of the memory cell array blocks is different, means for dividing down a chrominance subcarrier; and means responsive to said divided down chrominance subcarrier and a write/read enabling signal for deriving an internal clock signal, wherein said internal clock signal deriving mean include means for providing a write clock signal having a first activating timing for a data writing operation and providing a read clock signal having a second activating timing, different from said first activating timing, for a data reading operation; wherein said internal clock signal is applied in common to said plurality of register means, so that a shifting operation in each of said plurality of register means is performed in response to the same internal clock signal.

Claim 37

A video random access memory device (VRAM) for reading and writing pixel data, comprising: a memory cell array divided into a plurality of blocks, a plurality of register means each provided corresponding to each said plurality of blocks for receiving and sending data from and to memory cells on a selected row in the corresponding block, each of said plurality of register means including means for dat latching and shifting data, a plurality of input buffer means provided separately corresponding to each said plurality of register means for serially transmitting externally applied data to the corresponding register, said plurality of input buffer means receiving different data from each other in a sequential data stream, a plurality of output buffer means each provided corresponding to each of said plurality of register means for serially outputting the data received from the corresponding register means, wherein timing of the activation of the input buffer means and the output buffer means for each of the memory cell array blocks is different, means for dividing down a chrominance subcarrier; and means responsive to said divided down chrominance subcarrier and a write/read enabling signal for deriving an internal clock signal, wherein said internal clock signal deriving means include (i) means for providing a clock signal as said internal clock signal in synchronization with operation of a first activated output buffer means among said plurality of output buffer means in a data reading operation, and (ii) means for providing a clock signal as said internal clock signal in synchronization with operation of one input buffer means among said plurality of input means in a data writing operation; wherein said internal clock signal is applied in common to said plurality of register means, so that a shifting operation in each of said plurality of register means is performed in response to the same internal clock signal.

Claim 38

A video random access memory device (VRAM) for reading and writing pixel data, comprising: a memory cell array divided into a plurality of blocks, a plurality of register means each provided corresponding to each said plurality of blocks for receiving and sending data from and to memory cells on a selected row in the corresponding block, each of said plurality of register means including means for dat latching and shifting data, a plurality of input buffer means provided separately corresponding to each said plurality of register means for serially transmitting externally applied data to the corresponding register, said plurality of input buffer means receiving different data from each other in a sequential data stream, a plurality of output buffer means each provided corresponding to each of said plurality of register means for serially outputting the data received from the corresponding register means, wherein timing of the activation of the input buffer means and the output buffer means for each of the memory cell array blocks is different, means for dividing down a chrominance subcarrier; and means responsive to said divided down chrominance subcarrier and a write/read enabling signal for deriving an internal clock signal, wherein said internal clock signal deriving means include (i) means for providing a clock signal as said internal clock signal in synchronization with operation of a first activated output buffer means among said plurality of output buffer means in a data reading operation, and (ii) means for providing a clock signal as said internal clock signal in synchronization with operation of one input buffer means among said plurality of input means in a data writing operation; wherein said internal clock signal is applied in common to said plurality of register means, so that a shifting operation in each of said plurality of register means is performed in response to the same internal clock signal.

Claim 39

A video random access memory comprising: a first memory cell array having a plurality of memory cells, a first shift register for latching and shifting a series of read-out data in reading out the series of read-out data from a series of memory cells of said first memory cell array and for latching and shifting a series of written-in data in writing the series of written-in data into a series of memory cells of said first memory cell array; a first output buffer connected to an output node of said first shift register for providing the read-out data latched in said first register to an output node of said memory device, based on a first clock signal; a first input buffer receiving incoming data for providing selectively data to be written into the series of memory cells of said first memory cell array among said incoming data, based on a second clock signal; a second memory cell array having a plurality of memory cells, a second shift register for latching and shifting a series of read-out data in reading out the series of read-out data out of a series of memory cells of said second memory cell array and for latching and shifting a series of written-in data in writing the series of written-in data into a series of memory cells of said second memory cell array; a second output buffer connected to said second shift register for providing the read-out data latched in said second shift register to said output node of said memory device, based on a third clock signal delayed in the phase to said first clock signal; a second input buffer receiving the incoming data for providing selectively among the incoming data the data to be written into a series of memory cells of said second memory cell array to said second shift register, based on a fourth clock signal delayed in the phase to said second clock signal; means for generating a first control signal in phase with said first clock signal and thereby in synchronization with operation of said first output buffer in the data reading operation, for controlling the shifting of data latched in said first and second shift registers in reading out the data of the series of memory cells of said first memory cell array latched in said first shift register and the data of the series of memory cells of said second memory cell array latched in said second shift register; means for generating a second control signal for controlling the respective shiftings of data from said first and second input buffers to said first and second shift registers, said second control signal being in phase with said fourth clock signal; and means for generating said first and second clock signals by dividing down a chrominance subcarrier externally applied, whereby activating timing for the data reading operation provided by said first control signal is different from the activating timing for the data writing operation provided by said second control signal.

Claim 40

A video random access memory comprising: a first memory cell array having a plurality of memory cells, a first shift register for latching and shifting a series of read-out data in reading out the series of read-out data from a series of memory cells of said first memory cell array and for latching and shifting a series of written-in data in writing the series of written-in data into a series of memory cells of said first memory cell array; a first output buffer connected to an output node of said first shift register for providing the read-out data latched in said first register to an output node of said memory device, based on a first clock signal; a first input buffer receiving incoming data for providing selectively data to be written into the series of memory cells of said first memory cell array among said incoming data, based on a second clock signal; a second memory cell array having a plurality of memory cells, a second shift register for latching and shifting a series of read-out data in reading out the series of read-out data out of a series of memory cells of said second memory cell array and for latching and shifting a series of written-in data in writing the series of written-in data into a series of memory cells of said second memory cell array; a second output buffer connected to said second shift register for providing the read-out data latched in said second shift register to said output node of said memory device, based on a third clock signal delayed in the phase to said first clock signal; a second input buffer receiving the incoming data for providing selectively among the incoming data the data to be written into a series of memory cells of said second memory cell array to said second shift register, based on a fourth clock signal delayed in the phase to said second clock signal; means for generating a first control signal in phase with said first clock signal and thereby in synchronization with operation of said first output buffer in the data reading operation, for controlling the shifting of data latched in said first and second shift registers in reading out the data of the series of memory cells of said first memory cell array latched in said first shift register and the data of the series of memory cells of said second memory cell array latched in said second shift register; means for generating a second control signal for controlling the respective shiftings of data from said first and second input buffers to said first and second shift registers, said second control signal being in phase with said fourth clock signal; and means for generating said first and second clock signals by dividing down a chrominance subcarrier externally applied, whereby activating timing for the data reading operation provided by said first control signal is different from the activating timing for the data writing operation provided by said second control signal.

Claim 41

A video random access memory comprising: a first memory cell array having a plurality of memory cells, a first shift register for latching and shifting a series of read-out data in reading out the series of read-out data from a series of memory cells of said first memory cell array and for latching and shifting a series of written-in data in writing the series of written-in data into a series of memory cells of said first memory cell array; a first output buffer connected to an output node of said first shift register for providing the read-out data latched in said first register to an output node of said memory device, based on a first clock signal; a first input buffer receiving incoming data for providing selectively data to be written into the series of memory cells of said first memory cell array among said incoming data, based on a second clock signal; a second memory cell array having a plurality of memory cells, a second shift register for latching and shifting a series of read-out data in reading out the series of read-out data out of a series of memory cells of said second memory cell array and for latching and shifting a series of written-in data in writing the series of written-in data into a series of memory cells of said second memory cell array; a second output buffer connected to said second shift register for providing the read-out data latched in said second shift register to said output node of said memory device, based on a third clock signal delayed in the phase to said first clock a second input buffer receiving the incoming data for providing selectively among the incoming data the data to be written into a series of memory cells of said second memory cell array to said second shift register, based on a fourth clock signal delayed in the phase to said second clock signal; means for generating a first control signal in phase with said first clock signal, for controlling the shifting of data latched in said first and second shift registers in reading out the data of the series of memory cells of said first memory cell array latched in said first shift register and the data of the series of memory cells of said second memory cell array latched in said second shift register; means for generating a second control signal for controlling the respective shiftings of data from said first and second input buffers to said first and second shift registers, said second control signal being in phase with said fourth clock signal and in synchronization with operation of the second input buffer in the data writing operation; and means for generating said first and second clock signals by dividing down a chrominance subcarrier externally applied.

Claim 42

A video random access memory comprising: a first memory cell array having a plurality of memory cells, a first shift register for latching and shifting a series of read-out data in reading out the series of read-out data from a series of memory cells of said first memory cell array and for latching and shifting a series of written-in data in writing the series of written-in data into a series of memory cells of said first memory cell array; a first output buffer connected to an output node of said first shift register for providing the read-out data latched in said first register to an output node of said memory device, based on a first clock signal; a first input buffer receiving incoming data for providing selectively data to be written into the series of memory cells of said first memory cell array among said incoming data, based on a second clock signal; a second memory cell array having a plurality of memory cells, a second shift register for latching and shifting a series of read-out data in reading out the series of read-out data out of a series of memory cells of said second memory cell array and for latching and shifting a series of written-in data in writing the series of written-in data into a series of memory cells of said second memory cell array; a second output buffer connected to said second shift register for providing the read-out data latched in said second shift register to said output node of said memory device, based on a third clock signal delayed in the phase to said first clock a second input buffer receiving the incoming data for providing selectively among the incoming data the data to be written into a series of memory cells of said second memory cell array to said second shift register, based on a fourth clock signal delayed in the phase to said second clock signal; means for generating a first control signal in phase with said first clock signal, for controlling the shifting of data latched in said first and second shift registers in reading out the data of the series of memory cells of said first memory cell array latched in said first shift register and the data of the series of memory cells of said second memory cell array latched in said second shift register; means for generating a second control signal for controlling the respective shiftings of data from said first and second input buffers to said first and second shift registers, said second control signal being in phase with said fourth clock signal and in synchronization with operation of the second input buffer in the data writing operation; and means for generating said first and second clock signals by dividing down a chrominance subcarrier externally applied.