Patent US5504690A successfully refreshed from Google Patents.
US5504690A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Automatic logic designing method and system
Assignee: Hitachi Ltd
•
Filing: 1993-08-16
•
Granted: 1996-04-02
•
Expires: 2013-08-16
Abstract
Abstract An automatic logic designing method and system in which a control table describing a condition and a behavior corresponding to the condition which express the specification of a computer is inputted and processed in a processor so that a logic circuit having no redundancy which can be easily seen by the designer is designed at a high speed. The control table is converted into the logic circuit whose function is expressed by a detailed Boolean expression. In an instance, selector logics are allocated in consideration of the polarity of the logic. A redundancy detection process or a redundancy logic elimination process is executed for the redundancy logics designated by a redundancy indicate file. A signal name which can be easily understood by the logic designer is formed. An implementing system includes an input control table file, a functional structure converting section of a conditional equation and a behavioral structure, a regular logic expanding processing section, and a redundancy logic elimination processing section, so that the logic circuit formed is outputted to a Boolean expression file.
Inventors
- 👤 Naohiro Kageyama
- 👤 Toru Shonai
- 👤 Rikako Suzuki
- 👤 Takashi Okada
- 👤 Kazuhiko Iijima
- 👤 Hiroyuki Nakajima
- 👤 Chihei Miura
- 👤 Tsuguo Shimizu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 15:05
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
239 words
A method of designing a logic circuit using a computer comprising the steps of: a) inputting in the form of a table for hardware implementation a description of logic specification in which a setting condition of a signal and a behavior of the logic circuit are described in a corresponding relation to each other as a behavioral specification of the logic circuit each being composed of at least one equation described by combining at least one type of a constant, a variable, a logical operator, a relational operator and an arithmetic operator said behavior of the logic circuit which is executed when said signal setting condition is satisfied; b) forming a Boolean expression corresponding to a selector for selecting an output of a logic circuit constructing said behavior description as a data signal on the basis of a selection signal which is generated from a logic circuit corresponding to the equation constructing said setting condition description when said signal setting condition is satisfied; c) registering said condition and said relational operator and/or arithmetic operator as described in said condition and said behavior into a library which has previously been prepared and allocating a regular logic circuit corresponding to a function of the operator expressed by a Boolean expression; and d) detecting and eliminating a redundancy logic included in the logic circuit whose function is expressed by the Boolean expression and which includes the selector and the regular logic circuit.
Claim 2
Independent Claim
239 words
A method of designing a logic circuit using a computer comprising the steps of: a) inputting in the form of a table for hardware implementation a description of logic specification in which a setting condition of a signal and a behavior of the logic circuit are described in a corresponding relation to each other as a behavioral specification of the logic circuit each being composed of at least one equation described by combining at least one type of a constant, a variable, a logical operator, a relational operator and an arithmetic operator said behavior of the logic circuit which is executed when said signal setting condition is satisfied; b) forming a Boolean expression corresponding to a selector for selecting an output of a logic circuit constructing said behavior description as a data signal on the basis of a selection signal which is generated from a logic circuit corresponding to the equation constructing said setting condition description when said signal setting condition is satisfied; c) registering said condition and said relational operator and/or arithmetic operator as described in said condition and said behavior into a library which has previously been prepared and allocating a regular logic circuit corresponding to a function of the operator expressed by a Boolean expression; and d) detecting and eliminating a redundancy logic included in the logic circuit whose function is expressed by the Boolean expression and which includes the selector and the regular logic circuit.
Claim 3
Dependent Claim
88 words
A method according to claim 1, wherein said Boolean expression forming step b) includes steps of: constructing said selector from said table by a positive logic for making a high potential state of a signal line correspond to a truth value; constructing the selector from said table by a negative logic for making a low potential state of the signal line correspond to a truth value; and deciding either one of said selectors having a smaller number of gates and allocating the decided selector to the logic circuit.
Claim 4
Dependent Claim
47 words
A method according to claim 1, wherein in said regular logic circuit allocating step c), a general signal name which has previously been prepared in the regular logic circuit and information regarding said relational operator or said arithmetic operator are combined, thereby forming an internal signal name.
Claim 5
Dependent Claim
62 words
A method according to claim 1, wherein said redundancy logic detecting and eliminating step d) includes a step of executing a logical operation of the Boolean equation by using a predetermined logical value of a signal in the case where said signal having said predetermined value is inputted to the logic circuit and eliminating the redundancy logic included in said logic circuit.
Claim 6
Dependent Claim
53 words
A method according to claim 1, wherein said redundancy logic detecting and eliminating step d) includes a step of detecting a partial logic circuit in which a signal path is branched in the logic circuit and the branched signal paths are again joined and eliminating the redundancy logic of said partial logic circuit.
Claim 7
Dependent Claim
122 words
A method according to claim 5, wherein in said step of detecting the partial logic circuit in which a signal path in said logic circuit is divided into branched signal paths and the branched signal paths are again joined, comprising: referring to a logic structure table to store constructing data of said logic circuit expressed by a Boolean expression; generating an adjacent matrix of logic elements of a signal source and logic elements on a signal transferring side on the basis of a connecting relation among the logic elements expressed in said table, generating a power matrix of said adjacent matrix; and determining redundant logic elements to be eliminated from a detected reconvergent area on the basis of said power matrix formed.
Claim 8
Dependent Claim
43 words
A method according to claim 1, wherein said redundancy logic detecting and eliminating step d) includes a step of instructing a partial logic circuit included in the logic circuit by the user and eliminating the redundancy logic on the basis of said instruction.
Claim 9
Independent Claim
147 words
A method of designing a logic, comprising the steps of: inputting a table for hardware implementation in which a description of a setting condition of a signal and a description of a behavior of a logic circuit which is executed when said condition is satisfied each description including at least one equation composed of combination of at least one of a constant, a variable, a logical operator, a relational operator and an arithmetic operator and being described as a specification of the logic circuit are stored in a corresponding relation to each other; discriminating the setting condition and the behavioral description for the signal in said table, respectively; translating said setting condition and said behavioral description of the logic circuit discriminated by said discriminating step into an internal expression in the form of a language; and forming a logic circuit corresponding to said translated language by compiling.
Claim 10
Independent Claim
147 words
A method of designing a logic, comprising the steps of: inputting a table for hardware implementation in which a description of a setting condition of a signal and a description of a behavior of a logic circuit which is executed when said condition is satisfied each description including at least one equation composed of combination of at least one of a constant, a variable, a logical operator, a relational operator and an arithmetic operator and being described as a specification of the logic circuit are stored in a corresponding relation to each other; discriminating the setting condition and the behavioral description for the signal in said table, respectively; translating said setting condition and said behavioral description of the logic circuit discriminated by said discriminating step into an internal expression in the form of a language; and forming a logic circuit corresponding to said translated language by compiling.
Claim 11
Dependent Claim
57 words
A method according to claim 8, wherein in said table, a description column of said condition and a description column of said behavior are divided into a plurality of subcolumns, the conditions and behaviors described in said subcolumns are coupled in accordance with a predetermined rule, and a description format of the condition and behavior is constructed.
Claim 12
Dependent Claim
69 words
A method according to claim 9, wherein said table formed is inputted, each of the subcolumns of said inputted table and the rule among the subcolumns is discriminated, the setting condition of the signal which is obtained as a result of said discrimination and the behavioral description of the logic circuit are translated into the internal expression, and the logic circuit corresponding to the translated internal expression is formed.
Claim 13
Dependent Claim
68 words
A method according to claim 8, wherein a format in which the description of the setting condition of the signal and the description of the behavior of the logic circuit which is executed when said condition is satisfied have been made correspond to each other is displayed on a display screen, thereby enabling the user to visibly input a data to a relevant item of said displayed format.
Claim 14
Dependent Claim
200 words
A logic design system for interactively designing a logic circuit using a computer, comprising: file means for storing a table for hardware implementation in which a description of a setting condition of a signal and a description of a behavior of a logic circuit which is expressed by at least one equation and is executed when said condition is satisfied are made as a specification description of said logic circuit in a corresponding relation to each other, each description including at least one equation composed of combination of at least one of a constant, a variable, a logical operator, a relational operator and an arithmetic operator; and a processor coupled to receive said table from said file means into a work area, for executing a plurality of processes, wherein said processor comprises discriminating means for discriminating the description of the setting condition of the signal and said behavioral description for said table in accordance with a processing program; translating means for translating the description of the setting condition and the behavioral description of the logic circuit into an internal expression; and generating means for generating a logic circuit on design corresponding to the internal expression translated by said translating means.
Claim 15
Dependent Claim
200 words
A logic design system for interactively designing a logic circuit using a computer, comprising: file means for storing a table for hardware implementation in which a description of a setting condition of a signal and a description of a behavior of a logic circuit which is expressed by at least one equation and is executed when said condition is satisfied are made as a specification description of said logic circuit in a corresponding relation to each other, each description including at least one equation composed of combination of at least one of a constant, a variable, a logical operator, a relational operator and an arithmetic operator; and a processor coupled to receive said table from said file means into a work area, for executing a plurality of processes, wherein said processor comprises discriminating means for discriminating the description of the setting condition of the signal and said behavioral description for said table in accordance with a processing program; translating means for translating the description of the setting condition and the behavioral description of the logic circuit into an internal expression; and generating means for generating a logic circuit on design corresponding to the internal expression translated by said translating means.
Claim 16
Dependent Claim
77 words
A system according to claim 12, further including table forming means for interactively forming said table, wherein said table forming means includes a resource of a table format having a description column of the setting condition of the signal and the description column of the behavior of the corresponding logic circuit, a display apparatus to display said format, and an input device to describe into said display format, and a table is formed by said description input.
References Cited (Backward Citations)
US4703435A
Cited
US5029102A
Cited
JPS6491243A
Cited
US5005136A
Cited
JPH0253476A
Cited
US5274793A
Cited
US5299137A
Cited
US5287289A
Cited
US5359537A
Cited
US5258919A
Cited
US5331569A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-04-02 | 1999-10-02 | 2000-04-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-04-02 | 2003-10-02 | 2004-04-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-04-02 | 2007-10-02 | 2008-04-02 | $7700.00 | Window Closed / Lapsed |