Patent US5497478A successfully refreshed from Google Patents.
US5497478A
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Memory access system and method modifying a memory interleaving scheme so that data can be read in any sequence without inserting wait cycles
Assignee: Advantest Singapore Pte Ltd
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Filing: 1995-01-31
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Granted: 1996-03-05
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Expires: 2015-01-31
Abstract
Abstract A memory access system and method is provided to modify a memory interleaving scheme so that data can be read from a memory system in any sequence without inserting a waiting cycle. Even addressees are assigned to a first memory bank and odd addresses to a second memory bank. If a sequential address sequence is being provided, the first and second memory banks are read alternately. A third memory bank is provided which has the contents of both first and second memory banks. When an address sequence is detected that successively accesses either the first memory bank or the second memory bank, the access is switched to the third memory bank.
Inventors
- 👤 Koh Murata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 13:57
CPC Classifications
G; G11; G11C; G11C7/00; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31917; G01R31/31919; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0607
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
174 words
A memory system for outputting a sequence of digital words in response to a sequence of addresses comprising: a plurality of mutually independently operating memory banks for storing digital words, each said digital word being stored in association with an address of at least one of said plurality of memory banks; an auxiliary memory bank for storing a copy of at least some of said digital words stored within said plurality of memory banks, each of said at least some of said digital words being stored in association with an address of said auxiliary memory bank; means for selecting one memory bank from said plurality of memory banks and said auxiliary memory bank by selecting said auxiliary memory bank instead of one of said plurality of memory banks when two consecutive addresses of said sequence of addresses are associated with a single one of said plurality of memory banks; and access means for accessing a digital word stored in said one memory bank in accordance with a current address of said sequence of addresses.
Claim 2
Dependent Claim
174 words
A memory system for outputting a sequence of digital words in response to a sequence of addresses comprising: a plurality of mutually independently operating memory banks for storing digital words, each said digital word being stored in association with an address of at least one of said plurality of memory banks; an auxiliary memory bank for storing a copy of at least some of said digital words stored within said plurality of memory banks, each of said at least some of said digital words being stored in association with an address of said auxiliary memory bank; means for selecting one memory bank from said plurality of memory banks and said auxiliary memory bank by selecting said auxiliary memory bank instead of one of said plurality of memory banks when two consecutive addresses of said sequence of addresses are associated with a single one of said plurality of memory banks; and access means for accessing a digital word stored in said one memory bank in accordance with a current address of said sequence of addresses.
Claim 3
Dependent Claim
33 words
The system of claim 1, wherein said sequence of addresses is an arbitrary sequence and wherein said auxiliary memory bank stores all of said digital words stored within said plurality of memory banks.
Claim 4
Independent Claim
177 words
A method of outputting a sequence of digital words in response to a sequence of addresses comprising: storing said sequence of digital words in a plurality of memory banks, each said digital word being stored in association with an address of at least one of said plurality of memory banks the memory banks being accessed in an interleaving manner; storing at least some of said digital words in an auxiliary memory bank, each of said at least some of said digital words being stored in association with an address of said auxiliary memory bank; selecting one memory bank from said plurality of memory banks and said auxiliary memory bank by selecting said auxiliary memory bank instead of one of said plurality of memory banks when two consecutive addresses of said sequence of addresses are associated with a single one of said plurality of memory banks; accessing a digital word stored in said one memory bank according to a current address of said sequence of addresses; and outputting each digital word so accessed from said one memory bank.
Claim 5
Independent Claim
177 words
A method of outputting a sequence of digital words in response to a sequence of addresses comprising: storing said sequence of digital words in a plurality of memory banks, each said digital word being stored in association with an address of at least one of said plurality of memory banks the memory banks being accessed in an interleaving manner; storing at least some of said digital words in an auxiliary memory bank, each of said at least some of said digital words being stored in association with an address of said auxiliary memory bank; selecting one memory bank from said plurality of memory banks and said auxiliary memory bank by selecting said auxiliary memory bank instead of one of said plurality of memory banks when two consecutive addresses of said sequence of addresses are associated with a single one of said plurality of memory banks; accessing a digital word stored in said one memory bank according to a current address of said sequence of addresses; and outputting each digital word so accessed from said one memory bank.
Claim 6
Dependent Claim
33 words
The method of claim 3, wherein said sequence of addresses is an arbitrary sequence and wherein said auxiliary memory bank stores all of said digital words stored within said plurality of memory banks.
Claim 7
Dependent Claim
181 words
A memory system for outputting a sequence of digital words with a constant interval between any two consecutive digital words in response to a sequence of addresses comprising: a plurality of mutually independently operating memory banks for storing digital words, each said digital word being stored in association with an address of at least one of said plurality of memory banks; an auxiliary memory bank for storing a copy of at least some of said digital words stored within said plurality of memory banks, each of said at least some of said digital words being stored in association with an address of said auxiliary memory bank; selecting means for selecting one memory bank from said plurality of memory banks and said auxiliary memory bank by selecting said auxiliary memory bank instead of one of said memory banks if the time between consecutive accesses to said one memory bank does not exceed a predetermined time; and access means for accessing one of said digital words stored in said one memory bank in accordance with a current address of said sequence of addresses.
Claim 8
Dependent Claim
181 words
A memory system for outputting a sequence of digital words with a constant interval between any two consecutive digital words in response to a sequence of addresses comprising: a plurality of mutually independently operating memory banks for storing digital words, each said digital word being stored in association with an address of at least one of said plurality of memory banks; an auxiliary memory bank for storing a copy of at least some of said digital words stored within said plurality of memory banks, each of said at least some of said digital words being stored in association with an address of said auxiliary memory bank; selecting means for selecting one memory bank from said plurality of memory banks and said auxiliary memory bank by selecting said auxiliary memory bank instead of one of said memory banks if the time between consecutive accesses to said one memory bank does not exceed a predetermined time; and access means for accessing one of said digital words stored in said one memory bank in accordance with a current address of said sequence of addresses.
Claim 9
Dependent Claim
21 words
The system of claim 5, wherein said auxiliary memory bank stores each digital word stored within said plurality of memory banks.
Claim 10
Dependent Claim
67 words
The system of claim 5, wherein said auxiliary memory bank stores at least some of said digital words stored within said plurality of memory banks and wherein said sequence of digital words is known, the digital words stored in said auxilliary memory bank being the digital words that would be accessed within a time shorter than said predetermined time based upon the known sequence of digital words.
Claim 11
Dependent Claim
82 words
The system of claim 7 wherein said selecting means provides an output signal indicating that said auxiliary memory bank has been selected, said access means comprising: counting means interfaced to receive said output signal from said selecting means for counting each time said output signal is received from said selecting means, and said counting means being additionally interfaced with said auxiliary memory bank and for providing an output to said auxiliary memory bank representative of an address of said auxiliary memory bank.
Claim 12
Independent Claim
176 words
A method of outputting a sequence of digital words with a constant interval between consecutive digital words in response to a sequence of addresses comprising: storing said sequence of digital words in a plurality of memory banks, each said digital word being stored in association with an address of at least one of said plurality of memory banks, the memory banks being accessed in an interleaving manner; storing at least some of said digital words in an auxiliary memory bank, each of said at least some of said digital words being stored in association with an address of said auxiliary memory bank; selecting one memory bank from said plurality of memory banks and said auxiliary memory bank, said auxiliary memory bank being selected instead of one of said memory banks if the time between consecutive accesses to said one memory bank does not exceed a predetermined time; and accessing a digital word stored in said one memory bank according to a current address, said one memory bank outputting said digital word in response to said accessing.
Claim 13
Independent Claim
176 words
A method of outputting a sequence of digital words with a constant interval between consecutive digital words in response to a sequence of addresses comprising: storing said sequence of digital words in a plurality of memory banks, each said digital word being stored in association with an address of at least one of said plurality of memory banks, the memory banks being accessed in an interleaving manner; storing at least some of said digital words in an auxiliary memory bank, each of said at least some of said digital words being stored in association with an address of said auxiliary memory bank; selecting one memory bank from said plurality of memory banks and said auxiliary memory bank, said auxiliary memory bank being selected instead of one of said memory banks if the time between consecutive accesses to said one memory bank does not exceed a predetermined time; and accessing a digital word stored in said one memory bank according to a current address, said one memory bank outputting said digital word in response to said accessing.
Claim 14
Independent Claim
22 words
The method of claims 9, wherein said auxiliary memory bank stores each said digital word stored within said plurality of memory banks.
Claim 15
Dependent Claim
66 words
The method of claim 9, wherein said auxiliary memory bank stores at least some of said digital words stored within said plurality of memory banks and wherein said sequence of digital words is known, the digital words stored in said auxilliary memory bank being the digital words that are accessed within a time shorter than said predetermined time based upon the known sequence of digital words.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-03-05 | 1999-09-04 | 2000-03-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-03-05 | 2003-09-04 | 2004-03-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-03-05 | 2007-09-04 | 2008-03-05 | $7700.00 | Window Closed / Lapsed |