US5496764A
Expired / Lapsed
US
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Process for forming a semiconductor region adjacent to an insulating layer
Assignee: Motorola Solutions Inc
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Filing: 1994-07-05
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Granted: 1996-03-05
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Expires: 2014-07-05
Abstract
Abstract An insulating layer is formed over a first substrate. Trenches are formed within a second substrate, and those trenches are filled with an insulating layer. The two substrate are bonded at their insulating layers. The portion of the second substrate away from the trenches is removed to form semiconductor regions over the insulating layer of the first substrate. Embodiments of the present invention allow better thickness control for SOI regions and lower leakage current compared to SOI layers that use LOCOS-type field isolation.
Inventors
- 👤 Shih-Wei Sun
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 00:12
CPC Classifications
H; H10; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10W; H10W10/00; H10W10/01; H10W10/061; H10W10/10; H10W10/181; H10P90/1914; H10W10/011; H10W10/014; H10W10/17; Y; Y10; Y10S; Y10S148/00; Y10S148/012; Y10S148/135
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
182 words
A process for forming a semiconductor region adjacent to an insulating layer comprising the steps of: forming a first insulating layer over a first substrate; forming a doped region within a second substrate, wherein: the doped region has a first conductivity type;. the second substrate has a second conductivity type that is opposite the first conductivity type; and this step is performed before bonding the first and second substrates; forming a trench within a second substrate, wherein the trench is no wider than 1.0 micron; forming a second insulating layer within the trench; bonding the first and second substrates together such that the first and second insulating layers are adjacent to each other; and removing a portion of the second substrate to expose portions of the second insulating layer to form a first active region from the doped region and a second active region from the second substrate, wherein: the first active region has the first conductivity type and the second active region has the second conductivity type; and the first and second active regions lie on opposite sides of the trench.
Claim 2
Dependent Claim
182 words
A process for forming a semiconductor region adjacent to an insulating layer comprising the steps of: forming a first insulating layer over a first substrate; forming a doped region within a second substrate, wherein: the doped region has a first conductivity type;. the second substrate has a second conductivity type that is opposite the first conductivity type; and this step is performed before bonding the first and second substrates; forming a trench within a second substrate, wherein the trench is no wider than 1.0 micron; forming a second insulating layer within the trench; bonding the first and second substrates together such that the first and second insulating layers are adjacent to each other; and removing a portion of the second substrate to expose portions of the second insulating layer to form a first active region from the doped region and a second active region from the second substrate, wherein: the first active region has the first conductivity type and the second active region has the second conductivity type; and the first and second active regions lie on opposite sides of the trench.
Claim 3
Dependent Claim
40 words
The process of claim 1, wherein: the step of forming the trench is performed such that the first active region is formed from the doped region; and the step of forming the trench is performed after forming the doped region.
Claim 4
Dependent Claim
35 words
The process of claim 1, wherein the step of removing includes: polishing away most of the second substrate; and etching a remaining portion of the second substrate to expose portions of the second insulating layer.
Claim 5
Dependent Claim
18 words
The process of claim 1, wherein the trenches are formed to a depth no deeper than 3000 angstroms.
Claim 6
Dependent Claim
68 words
The process of claim 1, further comprising steps of: forming a gate electrode over at least one of the first and second active regions, wherein the at least one of the first and second active regions has a uniform thickness under the gate electrode; and forming source and drain regions within the at least one of the first and second active regions and adjacent to the gate electrode.
Claim 7
Dependent Claim
21 words
The process of claim 1, further comprising a step of planarizing the second insulating layer prior to the step of bonding.
Claim 8
Dependent Claim
40 words
The process of claim 6, further comprising a step of forming a third insulating layer over the second insulating layer between the steps of planarizing and bonding, wherein the third insulating layer has a thickness no thicker than 200 angstroms.
Claim 9
Dependent Claim
93 words
A process for forming a semiconductor region adjacent to an insulating layer comprising the steps of: forming a first insulating layer over a first substrate; forming trenches within a second substrate; forming a second insulating layer within the trenches and over the second substrate; planarizing the second insulating layer; bonding the first and second substrates together such that the first and second insulating layers are adjacent to each other; polishing the second substrate to remove most of the second substrate; and etching the second substrate to expose portions of the second insulating layer.
Claim 10
Dependent Claim
93 words
A process for forming a semiconductor region adjacent to an insulating layer comprising the steps of: forming a first insulating layer over a first substrate; forming trenches within a second substrate; forming a second insulating layer within the trenches and over the second substrate; planarizing the second insulating layer; bonding the first and second substrates together such that the first and second insulating layers are adjacent to each other; polishing the second substrate to remove most of the second substrate; and etching the second substrate to expose portions of the second insulating layer.
Claim 11
Dependent Claim
36 words
The process of claim 8, further comprising a step of forming a doped region within the second substrate prior to the step of bonding, wherein the doped region and the second substrate have opposite conductivity types.
Claim 12
Dependent Claim
25 words
The process of claim 8, wherein the steps of polishing and etching are performed to form a first active region and a second active region.
Claim 13
Dependent Claim
18 words
The process of claim 8, wherein the trenches are formed to a depth no deeper than 3000 angstroms.
Claim 14
Dependent Claim
68 words
The process of claim 10, further comprising steps of: forming a gate electrode over at least one of the first and second active regions, wherein the at least one of the first and second active regions has a uniform thickness under the gate electrode; and forming source and drain regions within the at least one of the first and second active regions and adjacent to the gate electrode.
Claim 15
Dependent Claim
40 words
The process of claim 8, further comprising a step of forming a third insulating layer over the second insulating layer between the steps of planarizing and bonding, wherein the third insulating layer has a thickness no thicker than 200 angstroms.
Claim 16
Dependent Claim
125 words
A process for forming a semiconductor region adjacent to an insulating layer comprising the steps of: forming a first insulating layer over a first substrate; forming trenches within a second substrate, wherein the trenches have a depth no deeper than 3000 angstroms; forming a second insulating layer within the trenches and over the second substrate; polishing the second insulating layer to form exposed portions of the second substrate; forming a third insulating layer over the exposed portions of the second substrate; bonding the first and second substrates together such that the first and third insulating layers are adjacent to each other; polishing the second substrate to remove most of the second substrate; and etching the second substrate to expose portions of the second insulating layer.
Claim 17
Dependent Claim
125 words
A process for forming a semiconductor region adjacent to an insulating layer comprising the steps of: forming a first insulating layer over a first substrate; forming trenches within a second substrate, wherein the trenches have a depth no deeper than 3000 angstroms; forming a second insulating layer within the trenches and over the second substrate; polishing the second insulating layer to form exposed portions of the second substrate; forming a third insulating layer over the exposed portions of the second substrate; bonding the first and second substrates together such that the first and third insulating layers are adjacent to each other; polishing the second substrate to remove most of the second substrate; and etching the second substrate to expose portions of the second insulating layer.
Claim 18
Dependent Claim
40 words
The process of claim 14, further comprising a step of forming a doped region within the second substrate prior to the step of forming the second insulating layer, wherein the doped region and the second substrate have opposite conductivity types.
Claim 19
Dependent Claim
18 words
The process of claim 14, wherein the trenches are formed to a depth no deeper than 1000 angstroms.
Claim 20
Dependent Claim
18 words
The process of claim 14, wherein the second insulating layer has a thickness no thicker than 200 angstroms.
Claim 21
Dependent Claim
48 words
The process of claim 14, wherein the steps of polishing and etching are performed to form a first active region and a second active region, wherein: the first and second active regions lie on opposite sides of one of the trenches that is no wider than 1.0 micron.
Claim 22
Dependent Claim
68 words
The process of claim 18, further comprising steps of: forming a gate electrode over at least one of the first and second active regions, wherein the at least one of the first and second active regions has a uniform thickness under the gate electrode; and forming source and drain regions within the at least one of the first and second active regions and adjacent to the gate electrode.
Claim 23
Dependent Claim
37 words
The process of claim 18, further comprising steps of: forming an MOS transistor within one of the first and second active regions; and forming a bipolar transistor within the other of the first and second active regions.
Claim 24
Dependent Claim
23 words
The process of claim 15, wherein the step of forming the doped region is performed prior to the step of forming the trenches.
Claim 25
Dependent Claim
22 words
The process of claim 15, wherein the step of forming the doped region is performed after the step of forming the trenches.
Claim 26
Dependent Claim
37 words
The process of claim 1, further comprising steps of: forming an MOS transistor within one of the first and second active regions; and forming a bipolar transistor within the other of the first and second active regions.
Claim 27
Dependent Claim
17 words
The process of claim 8, wherein the step of etching is performed using a dry etching technique.
Claim 28
Dependent Claim
34 words
The process of claim 24, wherein the step of etching comprises: etching the second substrate until an endpoint is detected; and etching the second substrate for a time period after the endpoint is detected.
Claim 29
Dependent Claim
23 words
The process of claim 9, wherein the step of forming the doped region is performed prior to the step of forming the trenches.
Claim 30
Dependent Claim
22 words
The process of claim 9, wherein the step of forming the doped region is performed after the step of forming the trenches.
Claim 31
Dependent Claim
37 words
The process of claim 10, further comprising steps of: forming an MOS transistor within one of the first and second active regions; and forming a bipolar transistor within the other of the first and second active regions.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-03-05 | 1999-09-04 | 2000-03-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-03-05 | 2003-09-04 | 2004-03-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-03-05 | 2007-09-04 | 2008-03-05 | $7700.00 | Window Closed / Lapsed |