US5495206A
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Fractional N frequency synthesis with residual error correction and method thereof
Assignee: Quarterhill Inc
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Filing: 1993-10-29
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Granted: 1996-02-27
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Expires: 2013-10-29
Abstract
Abstract A frequency synthesizer (107) utilizes a variable oscillator (114) the output of which is used as the frequency synthesizer output (115) and is fed to a digital divider (108). The output of the digital divider (108) feeds one input of a phase comparator (109). The other input of the phase comparator (109) is fed from a reference oscillator (116). A phase comparator (109) output controls the variable oscillator (114). The digital divider (108) has a division ratio that is varied with time by a multi accumulator fractional-N division system (112) such that the effective division ratio may be varied by non-integer steps. Due to the time varying division sequence applied to the digital divider (108) there is a residual spurious level on the output signal (115). A second digital sequence from the multiple accumulator fractional. N-division system (112) is generated to reduce this spurious level and is applied to the output of the phase comparator (109).
Inventors
- 👤 Alexander W. Hietala
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 20:37
CPC Classifications
H; H03; H03B; H03B1/00; H03B1/04; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/089; H03L7/0891; H03L7/0895; H03L7/0898; H03L7/16; H03L7/18; H03L7/197; H03L7/1974; H03L7/1976
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
262 words
A frequency synthesizer having a controllable oscillator for generating a first signal having a first frequency, the frequency synthesizer comprising: means for creating a divider sequence signal, the divider sequence signal containing a desired value and an error value, the means for creating comprises: means for accepting a frequency offset signal, first means for integrating the frequency offset signal, forming a first integrated signal and a first carry signal, second means for integrating the first integrated signal forming a second integrated signal and a second carry signal, first means for derivating the second carry signal, forming a derivated second carry signal, means for combining said derivated second carry signal with said first carry signal, forming a first combined signal, means for derivating said first combined signal, forming a first derivated combined signal, and means for combining said first derivated combined signal with a programmable divider frequency divider signal, creating a divider sequence signal; means for dividing the first frequency of the first signal, the means for dividing dependent upon the divider sequence signal and forming a first divided signal; means for detecting a difference in phase of a reference signal and the first divided signal and generating a phase difference signal; means for approximating an error contained in the first divided signal at least due in part to the error value in the divider sequence signal and forming a first error correction signal; and means for modulating the phase difference signal with the first error correction signal and generating a modulated signal having reduced residual error and for controlling the controllable oscillator.
Claim 2
Dependent Claim
262 words
A frequency synthesizer having a controllable oscillator for generating a first signal having a first frequency, the frequency synthesizer comprising: means for creating a divider sequence signal, the divider sequence signal containing a desired value and an error value, the means for creating comprises: means for accepting a frequency offset signal, first means for integrating the frequency offset signal, forming a first integrated signal and a first carry signal, second means for integrating the first integrated signal forming a second integrated signal and a second carry signal, first means for derivating the second carry signal, forming a derivated second carry signal, means for combining said derivated second carry signal with said first carry signal, forming a first combined signal, means for derivating said first combined signal, forming a first derivated combined signal, and means for combining said first derivated combined signal with a programmable divider frequency divider signal, creating a divider sequence signal; means for dividing the first frequency of the first signal, the means for dividing dependent upon the divider sequence signal and forming a first divided signal; means for detecting a difference in phase of a reference signal and the first divided signal and generating a phase difference signal; means for approximating an error contained in the first divided signal at least due in part to the error value in the divider sequence signal and forming a first error correction signal; and means for modulating the phase difference signal with the first error correction signal and generating a modulated signal having reduced residual error and for controlling the controllable oscillator.
Claim 3
Dependent Claim
21 words
A frequency synthesizer in accordance with claim 1 further comprising means for filtering, responsive to means for modulating, the modulated signal.
Claim 4
Dependent Claim
48 words
A frequency synthesizer in accordance with claim 1 wherein said means for approximating the error further comprises: means for combining the first integrated signal with the second integrated signal forming a second combined signal; and means for derivating said second combined signal forming said first error correction signal.
Claim 5
Dependent Claim
163 words
A fractional-N frequency synthesizer accepting a first signal to select a controllable oscillator output signal frequency by dividing the output signal frequency with a variable divisor divider controlled by a divider sequence signal from an accumulator network creating a divided signal, the divider sequence signal containing a desired value and an error value, the fractional-N synthesizer comprising: an error correction signal generator for approximating the error contained in the divider sequence signal and generating an error correction signal; a phase detector coupled to the divided signal output from the variable divisor divider for detecting a difference in phase of a reference signal and the divided signal and generating a phase difference signal; a modulator coupled to the phase difference signal output from the phase detector for modulating the phase difference signal with the error correction signal and generating a modulated signal having reduced residual error; and a controllable oscillator for accepting the modulated signal and generating an output signal having a predetermined frequency.
Claim 6
Dependent Claim
163 words
A fractional-N frequency synthesizer accepting a first signal to select a controllable oscillator output signal frequency by dividing the output signal frequency with a variable divisor divider controlled by a divider sequence signal from an accumulator network creating a divided signal, the divider sequence signal containing a desired value and an error value, the fractional-N synthesizer comprising: an error correction signal generator for approximating the error contained in the divider sequence signal and generating an error correction signal; a phase detector coupled to the divided signal output from the variable divisor divider for detecting a difference in phase of a reference signal and the divided signal and generating a phase difference signal; a modulator coupled to the phase difference signal output from the phase detector for modulating the phase difference signal with the error correction signal and generating a modulated signal having reduced residual error; and a controllable oscillator for accepting the modulated signal and generating an output signal having a predetermined frequency.
Claim 7
Dependent Claim
215 words
A fractional-N frequency synthesizer comprising: a controllable oscillator outputting a first signal having a first frequency and accepting a modulated signal for controlling the first frequency of the first signal; an accumulator network creating a divider sequence signal, the divider sequence signal containing a desired value and an error value; a divider having a signal input and a control input and a signal output, the first signal coupled to the signal input of the divider, the divider sequence signal coupled to the control input of the divider for controlling a variable divisor divider, the variable divisor divider for dividing the first frequency of the first signal and generating a first divided signal; an error correction signal generator for approximating an error contained in the divider sequence signal at least due in part to the error value in the divider sequence signal and generating an error correction signal; a phase detector coupled to the divided signal output from the variable divisor divider for detecting a difference in phase of a reference signal and the divided signal and generating a phase difference signal; and a modulator coupled to the phase difference signal output from the phase detector for modulating the phase difference signal with the error correction signal and generating the modulated signal having reduced residual error.
Claim 8
Dependent Claim
215 words
A fractional-N frequency synthesizer comprising: a controllable oscillator outputting a first signal having a first frequency and accepting a modulated signal for controlling the first frequency of the first signal; an accumulator network creating a divider sequence signal, the divider sequence signal containing a desired value and an error value; a divider having a signal input and a control input and a signal output, the first signal coupled to the signal input of the divider, the divider sequence signal coupled to the control input of the divider for controlling a variable divisor divider, the variable divisor divider for dividing the first frequency of the first signal and generating a first divided signal; an error correction signal generator for approximating an error contained in the divider sequence signal at least due in part to the error value in the divider sequence signal and generating an error correction signal; a phase detector coupled to the divided signal output from the variable divisor divider for detecting a difference in phase of a reference signal and the divided signal and generating a phase difference signal; and a modulator coupled to the phase difference signal output from the phase detector for modulating the phase difference signal with the error correction signal and generating the modulated signal having reduced residual error.
Claim 9
Independent Claim
146 words
A method of frequency synthesizing, the frequency synthesizer having a controllable oscillator for generating a first signal having a first frequency, the method comprising the steps of: creating a divider sequence signal, the divider sequence signal containing a desired value and an error value; dividing the frequency of the first signal, the step of dividing dependent upon the divider sequence signal and forming a first divided signal having a phase; detecting a difference in phase of a reference frequency and the divided signal and generating a phase difference signal; approximating an error contained in the first divided signal at least due in part to the error value in the divider sequence signal and forming a first error correction signal; and modulating the phase difference signal with the first error correction signal and generating a modulated signal having reduced residual error and for controlling the controllable oscillator.
Claim 10
Independent Claim
146 words
A method of frequency synthesizing, the frequency synthesizer having a controllable oscillator for generating a first signal having a first frequency, the method comprising the steps of: creating a divider sequence signal, the divider sequence signal containing a desired value and an error value; dividing the frequency of the first signal, the step of dividing dependent upon the divider sequence signal and forming a first divided signal having a phase; detecting a difference in phase of a reference frequency and the divided signal and generating a phase difference signal; approximating an error contained in the first divided signal at least due in part to the error value in the divider sequence signal and forming a first error correction signal; and modulating the phase difference signal with the first error correction signal and generating a modulated signal having reduced residual error and for controlling the controllable oscillator.
Claim 11
Dependent Claim
25 words
A method of frequency synthesizing in accordance with claim 6 further comprising a step of filtering, responsive to said step of modulating, the modulated signal.
Claim 12
Dependent Claim
116 words
A method of frequency synthesizing in accordance with claim 6 wherein said step of creating a divider sequence signal further comprises the steps of: accepting a frequency offset signal; integrating the frequency offset signal, forming a first integrated signal and a first carry signal; integrating the first integrated signal forming a second integrated signal and a second carry signal; derivating the second carry signal, forming a derivated second carry signal; combining said derivated second carry signal with said first carry signal, forming a first combined signal; derivating said first combined signal, forming a first derivated combined signal; and combining said first derivated combined signal with a programmable divider frequency divider signal, forming a divider sequence signal.
Claim 13
Dependent Claim
46 words
A method of frequency synthesizing in accordance with claim 8 wherein said step of approximating the error further comprises: combining the first integrated signal with the second integrated signal forming a second combined signal; and derivating said second combined signal forming said first error correction signal.
References Cited (Backward Citations)
US4024464A
Cited
US4179670A
Cited
US4204174A
Cited
EP0038520A1
Cited
US4573023A
Cited
US4686488A
Cited
US4800342A
Cited
US4758802A
Cited
US4815018A
Cited
US4743867A
Cited
US4810977A
Cited
US4870384A
Cited
EP0340870A2
Cited
US4816774A
Cited
US5038120A
Cited
WO1990012458A1
Cited
WO1991007824A1
Cited
EP0429217A2
Cited
EP0438867A2
Cited
US5055802A
Cited
US5093632A
Cited
US5166642A
Cited
US5339050A
Cited
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1999-02-26 | 1999-08-28 | 2000-02-27 | $2000.00 | Window Closed / Lapsed |
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