Latched accumulator fractional n synthesis with residual error reduction

Claim 2

A fractional-N latched accumulator synthesizer having reduced residual error and accepting a digital number to select a controllable oscillator output signal frequency by dividing the output signal frequency with a variable divisor divider controlled by carry output signals from latched accumulator networks to create a signal which is filtered by a loop filter, the fractional-N latched accumulator synthesizer comprising: means for generating a first latched output signal which is an integral of the digital number; means for generating a second latched output signal which is an integral of said first latched output signal; means for combining said first latched output signal and said second latched output signal to generate a residual error correction signal; and means for coupling said residual error correction signal to the loop filter.

Claim 3

A fractional-N latched accumulator synthesizer in accordance with claim 1 wherein said means for coupling further comprises means for differentiating said residual error control signal.

Claim 4

A fractional-N latched accumulator synthesizer in accordance with claim 1 wherein said means for combining further comprises means for delaying said first latched output signal.

Claim 5

A fractional-N synthesizer having reduced residual error and accepting a digital number of a plurality of bits to select a controllable oscillator output signal frequency and which divides the output signal frequency with a loop divider, the loop divider having a variable divisor controlled by a control input signal to create a signal to be compared to a reference signal, the resulting feedback signal being filtered by a loop filter, the fractional-N synthesizer comprising: means for producing a clock signal; means for deriving at least a first integral of the digital number and generating a first latched output signal and a first carry output signal on a first occurrence of said clock signal; means for integrating said first latched output signal and generating a second carry output signal and a second latched output signal on a second occurrence of said clock signal; means for delaying said first carry output signal until a third occurrence of said clock signal; means for differentiating said second carry output signal; means for generating the control input signal from said delayed first carry output signal and said differentiated second carry output signal; means for combining said first latched output signal and said second latched output signal to generate a residual error correction signal; and means for coupling said residual error correction signal to the loop filter.

Claim 6

A fractional-N synthesizer having reduced residual error and accepting a digital number of a plurality of bits to select a controllable oscillator output signal frequency and which divides the output signal frequency with a loop divider, the loop divider having a variable divisor controlled by a control input signal to create a signal to be compared to a reference signal, the resulting feedback signal being filtered by a loop filter, the fractional-N synthesizer comprising: means for producing a clock signal; means for deriving at least a first integral of the digital number and generating a first latched output signal and a first carry output signal on a first occurrence of said clock signal; means for integrating said first latched output signal and generating a second carry output signal and a second latched output signal on a second occurrence of said clock signal; means for delaying said first carry output signal until a third occurrence of said clock signal; means for differentiating said second carry output signal; means for generating the control input signal from said delayed first carry output signal and said differentiated second carry output signal; means for combining said first latched output signal and said second latched output signal to generate a residual error correction signal; and means for coupling said residual error correction signal to the loop filter.

Claim 7

A fractional-N synthesizer in accordance with claim 4 wherein said means for coupling further comprises means for differentiating said residual error control signal.

Claim 8

A fractional-N synthesizer in accordance with claim 4 wherein said means for combining further comprises means for delaying said first latched output signal.

Claim 9

A fractional-N synthesizer in accordance with claim 4 wherein said means for combining further comprises means for delaying said first latched output signal until said second occurrence of said clock signal.

Claim 10

A radio transmitter employing a fractional-N synthesizer having reduced residual error and accepting a digital number of a plurality of bits to select a frequency for an operating signal and dividing the output signal frequency with a loop divider, the loop divider having a variable divisor controlled by a control input signal to create a signal to be compared to a reference signal, the resulting feedback signal being filtered by a loop filter, the radio transmitter comprising: means for producing a clock signal; means for deriving at least a first integral of the digital number and generating a first latched output signal and a first carry output signal on a first occurrence of said clock signal; means for integrating said first latched output signal and generating a second carry output signal and a second latched output signal on a second occurrence of said clock signal; means for delaying said first carry output signal until a third occurrence of said clock signal; means for differentiating said second carry output signal; means for generating the control input signal from said delayed first carry output signal and said differentiated second carry output signal; means for combining said first latched output signal and said second latched output signal to generate a residual error correction signal; means for coupling said residual error correction signal to the loop filter; means, responsive to the control input signal and the coupled residual error signal, for generating the operating signal with reduced residual error; and means for transmitting the operating signal.

Claim 11

A radio transmitter employing a fractional-N synthesizer having reduced residual error and accepting a digital number of a plurality of bits to select a frequency for an operating signal and dividing the output signal frequency with a loop divider, the loop divider having a variable divisor controlled by a control input signal to create a signal to be compared to a reference signal, the resulting feedback signal being filtered by a loop filter, the radio transmitter comprising: means for producing a clock signal; means for deriving at least a first integral of the digital number and generating a first latched output signal and a first carry output signal on a first occurrence of said clock signal; means for integrating said first latched output signal and generating a second carry output signal and a second latched output signal on a second occurrence of said clock signal; means for delaying said first carry output signal until a third occurrence of said clock signal; means for differentiating said second carry output signal; means for generating the control input signal from said delayed first carry output signal and said differentiated second carry output signal; means for combining said first latched output signal and said second latched output signal to generate a residual error correction signal; means for coupling said residual error correction signal to the loop filter; means, responsive to the control input signal and the coupled residual error signal, for generating the operating signal with reduced residual error; and means for transmitting the operating signal.

Claim 12

A radio transmitter in accordance with claim 8 wherein said means for coupling further comprises means for differentiating said residual error control signal.

Claim 13

A radio transmitter in accordance with claim 8 wherein said means for combining further comprises means for delaying said first latched output signal until said second occurrence of said clock signal.

Claim 14

A radio transmitter in accordance with claim 8 further comprising means for modulating the operating signal by time varying at least one bit of said digital number.

Claim 15

A radio transmitter in accordance with claim 8 wherein the variable divisor has an average value represented by the sum of an integer and a quotient of a numerator divided by a denominator.

Claim 16

A radio transmitter in accordance with claim 12 wherein said denominator of the variable divisor is of a large value such that the frequency of the quotient of the reference signal divided by said denominator is much less than the corner frequency of a highpass characteristic of the fractional-N synthesizer whereby spurious signals in the operating signal are rejected.

Claim 17

A radio transmitter in accordance with claim 12 further comprising means for maintaining said denominator for a multiplicity of numerator values by selecting a predetermined state for at least one bit of said digital number.

Claim 20

A method in accordance with the method of claim 15 further comprising the step of differentiating said residual error control signal.

Claim 21

A method in accordance with the method of claim 15 wherein said step of combining further comprises the step of delaying said first latched output signal.