Digital frequency synthesizer and digital modulator using same

Claim 2

Digital frequency synthesizer providing an output signal whose output frequency f1 is a function of the clock frequency f2 of a clock signal (CL1) and of a digital frequency value of an input signal, characterized in that it is of the type performing a fractional multiplication of said clock frequency f2, said output frequency f1 being equal to the product of said clock frequency f2 and a factor equal to the sum (N + F + M; N′ + (F′+M)/P) of an integer value (N; N′) and a rational number (F+M; (F′+M)/P) itself equal to the sum of a first fractional part of unity (F; F′) and a second fractional part of unity (M; M/P) which is said digital frequency value.

Claim 3

Digital frequency synthesizer according to claim 1, characterized in that it includes further means to multiply said factor by a second integer (P) and that the magnitude of said rational number [(F′+M)/P] is smaller than unity.

Claim 4

Digital frequency synthesizer according to claim 2, c.i.t. for a predetermined range of said output frequency f1 extending from a minimum f11 to a maximum f12 f12 - Pf2 < N′ Pf2 <= f11 and f12 - f11 < Pf2 wherein N′ and P are said first and second integers respectively.

Claim 5

Digital frequency synthesizer according to claim 3, c.i.t. said first integer (N′) is constant for all output frequencies of said range.

Claim 6

Digital frequency synthesizer according to claim 2, c.i.t. said first integer (N′) is a power of 2.

Claim 7

Digital frequency synthesizer according to claim 2, c.i.t. said first integer (N′) is equal to 1.

Claim 8

Digital frequency synthesizer according to claim 2, c.i.t. said second integer (P) is a power of 2.

Claim 9

Digital frequency synthesizer according to claim 2, characterized in that it includes an accumulator means (ACC, REG3/4) which is controlled by said clock signal (CLI), calculates an accumulated value which is function of said rational number (F′+M)/P and provides an activated control signal each time the integer part of said accumulated value reaches a predetermined value, as well as a phase-locked loop whose forward path is controlled by said clock signal (CLI) and includes the cascade connection of at least a phase detector (PD) and a controlled oscillator (VCO) providing said output signal (SO) and the feedback path (DIV2, CRC, DIV3) of which includes the cascade connection of at least a first divider circuit (DIV2) dividing by said second integer (P), a single cycle control circuit (CRC) controlled by the output signal of said accumulator means and a second divider circuit (DIV2) dividing by said first integer (N′).

Claim 10

Digital frequency synthesizer according to claim 1, characterized in that it includes an accumulator (ACC) which is controlled by said clock signal (CLI), calculates the accumulated algebraic value of said rational number (F + M) and provides at least one first control signal (S1/3) which is function of the integer part (0, 1, 2) of said accumulated value, as well as a phase-locked loop whose forward path (PD, S, LF, VCO) is controlled by said clock signal (CLI) and includes the cascade connection of at least a phase detector (PD) and a controlled oscillator (VCO) providing said output signal (SO) and the feedback path (CRC, DIV1) of which includes the cascade connection of at least a cycle removing circuit (CRC) able to remove cycles from said output signal and a divider circuit (DIV1), said cycle removing circuit (CRC) being controlled by said first control signal (S1/3) and said divider circuit (DIV1) being controlled by a second control signal which is a function (N-1) of said integer value (N), that said first fractional part (F) and the absolute value of said second fractional part (M) are each larger than or equal to zero and smaller than 1, and that said accumulator (ACC) has first (F) and second (SI) inputs for said first (F) and second (M) fractional parts and is provided with a number of outputs (S1/3) which are activated for distinct values (0, 1, 2) of said integer part of said accumulated algebraic value.

Claim 11

Digital modulator characterized by a digital frequency synthesizer according to any of the claims 1 to 9.

Claim 12

Digital modulator according to any of the claims 1 to 8 and to claim 10, characterized in that MF2 is a modulating input signal, that f′ = kF′ and M = kM with f′ and k being positive integers, m a positive or negative integer and with k larger than f′ and larger than m, and that the values of f′ and m are added in a summing circuit (SUM) before being applied to said accumulator (ACC) for which said predetermined value is equal to kP.