US5494849A
Expired / Lapsed
US
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Single-etch stop process for the manufacture of silicon-on-insulator substrates
Assignee: Si Bond LLC
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Filing: 1995-03-23
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Granted: 1996-02-27
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Expires: 2015-03-23
Abstract
Abstract A single-etch stop process for the manufacture of silicon-on-insulator substrates. The process includes forming a silicon-on-insulator bonded substrate comprising a handle wafer, a device wafer, a device layer having a thickness of between about 0.5 and 50 micrometers, and an oxide layer with the device layer being between the device wafer and the oxide layer and the oxide layer being between the device layer and the handle wafer, the device wafer having a boron concentration of at least about 1×10 18 boron atoms/cm 3 and a resistivity of about 0.01 to about 0.02 ohm-cm. A portion of the device wafer is mechanically removed from the silicon-on-insulator bonded substrate wherein the device wafer has a total thickness variation across the surface of the wafer of less than about 2 micrometers and a defect-free surface after the mechanical removal step. The defect-free surface of the device wafer is thereafter etched away to expose the device layer, and the exposed device layer is polished to produce a silicon-on-insulator substrate having a device layer the total thickness variation of which does not exceed 10% of the maximum thickness of the device layer.
Inventors
- 👤 Subramanian S. Iyer
- 👤 Emil Baran
- 👤 Mark L. Mastroianni
- 👤 Robert A. Craven
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 03:34
CPC Classifications
H; H10; H10P; H10P36/00; H10P36/03; H10P36/07; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10P90/1914; H10W; H10W10/00; H10W10/10; H10W10/181; Y; Y10; Y10S; Y10S148/00; Y10S148/012; Y10S148/135
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
179 words
A single-etch stop process for the manufacture of silicon-on-insulator substrates comprising forming a silicon-on-insulator bonded substrate comprising a handle wafer, a device wafer, a device layer having a thickness of between about 0.5 and 50 micrometers, and an oxide layer with the device layer being between the device wafer and the oxide layer and the oxide layer being between the device layer and the handle wafer, the device wafer having a boron concentration of at least about 1×10 18 boron atoms/cm 3 and a resistivity of about 0.01 to about 0.02 ohm-cm, removing a portion of the device wafer from the silicon-on-insulator bonded substrate, the device wafer having a total thickness variation across the surface of the wafer of less than about 2 micrometers and a defect-free surface after the removal step, etching away the defect-free surface of the device wafer to expose the device layer, and polishing the exposed device layer to produce a silicon-on-insulator substrate having a device layer the total thickness variation of which does not exceed 10% of the maximum thickness of the device layer.
Claim 2
Dependent Claim
179 words
A single-etch stop process for the manufacture of silicon-on-insulator substrates comprising forming a silicon-on-insulator bonded substrate comprising a handle wafer, a device wafer, a device layer having a thickness of between about 0.5 and 50 micrometers, and an oxide layer with the device layer being between the device wafer and the oxide layer and the oxide layer being between the device layer and the handle wafer, the device wafer having a boron concentration of at least about 1×10 18 boron atoms/cm 3 and a resistivity of about 0.01 to about 0.02 ohm-cm, removing a portion of the device wafer from the silicon-on-insulator bonded substrate, the device wafer having a total thickness variation across the surface of the wafer of less than about 2 micrometers and a defect-free surface after the removal step, etching away the defect-free surface of the device wafer to expose the device layer, and polishing the exposed device layer to produce a silicon-on-insulator substrate having a device layer the total thickness variation of which does not exceed 10% of the maximum thickness of the device layer.
Claim 3
Dependent Claim
37 words
A process as set forth in claim 1 wherein the step of removing a portion of the device wafer comprises a two-stage process in which a coarse material removal stage is followed by a smooth grinding stage.
Claim 4
Dependent Claim
19 words
A process as set forth in claim 2 wherein the coarse material removing stage comprises chemically etching or grinding.
Claim 5
Dependent Claim
33 words
A process as set forth in claim 2 wherein the step of removing a portion of the device wafer additionally comprises polishing the surface of the device wafer after the smooth grinding stage.
Claim 6
Dependent Claim
52 words
A process as set forth in claim 1 wherein the step of etching away the defect-free surface of the device wafer comprises immersing the silicon-on-insulator bonded substrate in a bath containing hydrofluoric acid, nitric acid and acetic acid and reconditioning the bath by adding peroxide, ozone or other oxidant to the bath.
Claim 7
Dependent Claim
76 words
A process as set forth in claim 1 wherein the step of etching away the defect-free surface of the device wafer comprises immersing the silicon-on-insulator bonded substrate in a bath containing hydrofluoric acid, nitric acid and acetic acid and, after the etch rate begins to diminish, withdrawing the silicon-on-insulator bonded substrate from the bath, reactivating the device wafer surface, and reimmersing the silicon-on-insulator bonded substrate in the bath containing hydrofluoric acid, nitric acid and acetic acid.
Claim 8
Dependent Claim
26 words
A process as set forth in claim 6 wherein the device wafer surface is reactivated by being exposed to air or by being immersed in water.
Claim 9
Dependent Claim
39 words
A process as set forth in claim 6 wherein the steps of reactivating the device wafer surface and reimmersing the silicon-on-insulator bonded substrate in the bath containing hydrofluoric acid, nitric acid and acetic acid are repeated at least twice.
Claim 10
Dependent Claim
26 words
A process as set forth in claim 8 wherein the device wafer surface is reactivated by being exposed to air or by being immersed in water.
Claim 11
Dependent Claim
24 words
A process as set forth in claim 8 wherein the surface is reactivated by immersing the surface in water and the water contains ozone.
Claim 12
Dependent Claim
22 words
A process as set forth in claim 1 wherein the exposed device layer is polished using an ammonia stabilized colloidal silica slurry.
Claim 13
Dependent Claim
26 words
A process as set forth in claim 1 wherein no more than about 200 nm of silicon are removed when the exposed device layer is polished.
Claim 14
Dependent Claim
40 words
A process as set forth in claim 1 wherein the thickness of the device wafer after the step of mechanically removing a portion of the device wafer from the silicon-on-insulator bonded substrate is between about 10 and about 30 micrometers.
Claim 15
Dependent Claim
21 words
A process as set forth in claim 1 wherein the periphery of the bonded silicon-on-insulator bonded substrate is abraded by grinding.
Claim 16
Dependent Claim
38 words
A process as set forth in claim 1 wherein the silicon-on-insulator bonded substrate is subjected to a high temperature annealing step to increase the bonding strength after the device wafer is etched away to expose the device layer.
Claim 17
Dependent Claim
238 words
A single-etch stop process for the manufacture of silicon-on-insulator substrates comprising forming a silicon-on-insulator bonded substrate comprising a handle wafer, a device wafer, a device layer having a thickness of between about 0.5 and 50 micrometers, and an oxide layer with the device layer being between the device wafer and the oxide layer and the oxide layer being between the device layer and the handle wafer, the device wafer having a boron concentration of at least about 1×10 18 boron atoms/cm 3 and a resistivity of about 0.01 to about 0.02 obm-cm, grinding away a portion of the device wafer from the silicon-on-insulator bonded substrate and polishing the ground surface of the device wafer, the device wafer having a thickness of between about 10 and about 30 micrometers, a total thickness variation across the surface of the wafer of less than about 2 micrometers, and a defect-free surface after the ground surface is polished, etching away the defect-free surface of the device wafer to expose the device layer, and polishing the exposed device layer using an ammonia stabilized colloidal silica slurry to produce a silicon-on-insulator substrate having a device layer the total thickness variation of which does not exceed 10% of the maximum thickness of the device layer, the amount of silicon being removed from the exposed device layer during the polishing step being no more than about 200 nm of the thickness of the exposed device layer.
Claim 18
Dependent Claim
238 words
A single-etch stop process for the manufacture of silicon-on-insulator substrates comprising forming a silicon-on-insulator bonded substrate comprising a handle wafer, a device wafer, a device layer having a thickness of between about 0.5 and 50 micrometers, and an oxide layer with the device layer being between the device wafer and the oxide layer and the oxide layer being between the device layer and the handle wafer, the device wafer having a boron concentration of at least about 1×10 18 boron atoms/cm 3 and a resistivity of about 0.01 to about 0.02 obm-cm, grinding away a portion of the device wafer from the silicon-on-insulator bonded substrate and polishing the ground surface of the device wafer, the device wafer having a thickness of between about 10 and about 30 micrometers, a total thickness variation across the surface of the wafer of less than about 2 micrometers, and a defect-free surface after the ground surface is polished, etching away the defect-free surface of the device wafer to expose the device layer, and polishing the exposed device layer using an ammonia stabilized colloidal silica slurry to produce a silicon-on-insulator substrate having a device layer the total thickness variation of which does not exceed 10% of the maximum thickness of the device layer, the amount of silicon being removed from the exposed device layer during the polishing step being no more than about 200 nm of the thickness of the exposed device layer.
Claim 19
Dependent Claim
38 words
A process as set forth in claim 16 wherein the silicon-on-insulator bonded substrate is subjected to a high temperature annealing step to increase the bonding strength after the device wafer is etched away to expose the device layer.
Claim 20
Dependent Claim
76 words
A process as set forth in claim 16 wherein the step of etching away the defect-free surface of the device wafer comprises immersing the silicon-on-insulator bonded substrate in a bath containing hydrofluoric acid, nitric acid and acetic acid and, after the etch rate begins to diminish, withdrawing the silicon-on-insulator bonded substrate from the bath, reactivating the device wafer surface, and reimmersing the silicon-on-insulator bonded substrate in the bath containing hydrofluoric acid, nitric acid and acetic acid.
Claim 21
Dependent Claim
26 words
A process as set forth in claim 18 wherein the device wafer surface is reactivated by being exposed to air or by being immersed in water.
Claim 22
Dependent Claim
39 words
A process as set forth in claim 18 wherein the steps of reactivating the device wafer surface and reimmersing the silicon-on-insulator bonded substrate in the bath containing hydrofluoric acid, nitric acid and acetic acid are repeated at least twice.
Claim 23
Dependent Claim
64 words
A process for etching silicon from the surface of a substrate in an etchant comprising hydrofluoric acid, nitric acid and acetic acid, the process comprising contacting the surface with the etchant and, after the etch rate begins to diminish, reactivating the surface by exposing the surface to air or by immersing the surface in water and thereafter again contacting the surface with the etchant.
Claim 24
Dependent Claim
64 words
A process for etching silicon from the surface of a substrate in an etchant comprising hydrofluoric acid, nitric acid and acetic acid, the process comprising contacting the surface with the etchant and, after the etch rate begins to diminish, reactivating the surface by exposing the surface to air or by immersing the surface in water and thereafter again contacting the surface with the etchant.
Claim 25
Dependent Claim
26 words
A process as set forth in claim 21 wherein the surface is reactivated by immersing the surface in water and the water contains oxygen or ozone.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-02-26 | 1999-08-28 | 2000-02-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-02-26 | 2003-08-28 | 2004-02-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-02-26 | 2007-08-28 | 2008-02-27 | $7700.00 | Window Closed / Lapsed |