Patent US5494838A successfully refreshed from Google Patents.
US5494838A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process of making EEPROM memory device having a sidewall spacer floating gate electrode
Assignee: Motorola Solutions Inc
•
Filing: 1995-05-23
•
Granted: 1996-02-27
•
Expires: 2015-05-23
Abstract
Abstract An EEPROM memory array includes a plurality of memory cells having a floating gate electrode (22) formed as a sidewall spacer adjacent to a control gate electrode (20). Source and drain regions (12, 14) reside in a semiconductor substrate (10) and define a segmented channel region (16) therebetween. A select gate electrode (18) overlies a first channel region (24) and separates the floating gate electrode (2) from the source region (12). The control gate electrode (20) overlies a third channeI region (28) and separates the floating gate electrode (22) from the drain region (14). The floating gate electrode (22) overlies a second channel region (26) and is separated therefrom by a thin tunnel oxide layer (42). The EEPROM device of the invention can be programmed by either source side injection, or by Fowler-Nordheim tunneling. Additionally, a process is provided for the fabrication of an EEPROM array utilizing adjacent select gate electrodes (18, 18') as a doping mask.
Inventors
- 👤 Kuo-Tung Chang
- 👤 Umesh Sharma
- 👤 Jack Higman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 18:09
CPC Classifications
H; H10; H10B; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/6891; H10D30/6892
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
140 words
Method for fabricating an EEPROM memory array comprising the steps of: providing a semiconductor substrate having an active region therein; forming first and second oxide encapsulated control gate electrodes overlying the active region; forming a tunnel oxide layer overlying the substrate intermediate to the first and second control gate electrodes; forming floating-gate sidewall spacers adjacent to the first and second control gate electrodes and overlying a portion of the tunnel oxide layer; forming an insulating layer overlying the first and second control gate electrodes and the floating-gate sidewall spacers; forming first and second select gate electrodes intermediate to sidewall spacers and separated therefrom by the insulating layer; and doping the substrate to form a source in the semiconductor substrate intermediate to the first and second floating gate electrodes, using the first and second select gate electrodes as a doping mask.
Claim 2
Dependent Claim
140 words
Method for fabricating an EEPROM memory array comprising the steps of: providing a semiconductor substrate having an active region therein; forming first and second oxide encapsulated control gate electrodes overlying the active region; forming a tunnel oxide layer overlying the substrate intermediate to the first and second control gate electrodes; forming floating-gate sidewall spacers adjacent to the first and second control gate electrodes and overlying a portion of the tunnel oxide layer; forming an insulating layer overlying the first and second control gate electrodes and the floating-gate sidewall spacers; forming first and second select gate electrodes intermediate to sidewall spacers and separated therefrom by the insulating layer; and doping the substrate to form a source in the semiconductor substrate intermediate to the first and second floating gate electrodes, using the first and second select gate electrodes as a doping mask.
Claim 3
Dependent Claim
87 words
The method of claim 1, wherein the step of forming semiconductor sidewall spacers comprises the steps of: depositing a layer of semiconductor material to overlie the first and second control gate electrodes; anisotropically etching the semiconductor layer to form sidewall spacers adjacent to the first and second control gate electrodes; forming an etching mask to protect a portion of the active region and a portion of the sidewall spacers intermediate to the first and second control gate electrodes; and etching away unprotected portions of the sidewall spacers.
Claim 4
Dependent Claim
81 words
The method of claim 1, wherein the step of forming first and second select gate electrodes comprises the steps of: depositing a layer of semiconductor material to overlie the insulating layer; and etching the semiconductor layer to form first and second opposing portions thereof, wherein each opposing portion overlies a portion of the active region, the sidewall spacer, and a portion of the control gate electrode, and wherein each opposing portion is separated from the active region by the insulating layer.
Claim 5
Dependent Claim
64 words
The method of claim 1, wherein the step of forming first and second select gate electrodes comprises the steps of: depositing a layer of semiconductor material to overlie the insulating layer; and anisotropically etching the semiconductor layer to form sidewall spacers overlying a portion of the active region adjacent to the floating-gate sidewall spacers and separated from the active region by the insulating layer.
References Cited (Backward Citations)
JPS6243179A
Cited
JPS6345862A
Cited
US5020030A
Cited
US5296396A
Cited
US5051793A
Cited
US5194925A
Cited
US5063172A
Cited
US5108939A
Cited
US5338952A
Cited
US5225362A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-02-26 | 1999-08-28 | 2000-02-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-02-26 | 2003-08-28 | 2004-02-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-02-26 | 2007-08-28 | 2008-02-27 | $7700.00 | Window Closed / Lapsed |