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US5493664A
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Microcomputer that transfers address and control to a debugging routine when an input address is a breakpoint address and a user accessible register for signalling if the breakpoint address is from the cache memory or a main memory
Assignee: Mitsubishi Electric Corp
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Filing: 1993-01-15
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Granted: 1996-02-20
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Expires: 2013-01-15
Abstract
Abstract A processor according to the present invention includes a user-accessible 1 bit register for indicating, upon instruction breaking or data breaking occurring, whether any instruction or data to be debugged is existent in a cache memory or in a memory, and the 1 bit register possesses a bit issued correspondingly to a hit signal issued from the cache memory, whereby it can be known with each whether the instruction or data is existent in the cache memory or in the memory.
Inventors
- 👤 Toshio Doi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 13:58
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/3648
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
223 words
A microcomputer, including a processor for executing instructions, said microcomputer comprising: a main memory for storing therein a plurality of instructions; a cache memory, coupled to said main memory, for storing therein a subset of the plurality of instructions stored in said memory, where the processor specifies an address of an instruction to be executed and executes an instruction provided by said cache memory when the instruction to be executed is included in the subset stored in said cache memory and executes an instruction provided by said main memory otherwise; a memory controller, coupled to the cache, for issuing a hit signal when an instruction to be executed is provided by said cache memory; an instruction break pointer, coupled to receive the address of an instruction to be executed, for transferring control to a debugging routine when the address of an instruction to be executed is a breakpoint address held by said instruction break pointer; and a user-accessible register, coupled to said memory controller and responsive to said hit signal, for holding a bit indicating whether an instruction to be executed is provided by said cache memory or said main memory so that the accessible register indicates whether an instruction specified by said breakpoint address is provided by said cache memory or said main memory when control is transferred to the debugging routine.
Claim 2
Dependent Claim
223 words
A microcomputer, including a processor for executing instructions, said microcomputer comprising: a main memory for storing therein a plurality of instructions; a cache memory, coupled to said main memory, for storing therein a subset of the plurality of instructions stored in said memory, where the processor specifies an address of an instruction to be executed and executes an instruction provided by said cache memory when the instruction to be executed is included in the subset stored in said cache memory and executes an instruction provided by said main memory otherwise; a memory controller, coupled to the cache, for issuing a hit signal when an instruction to be executed is provided by said cache memory; an instruction break pointer, coupled to receive the address of an instruction to be executed, for transferring control to a debugging routine when the address of an instruction to be executed is a breakpoint address held by said instruction break pointer; and a user-accessible register, coupled to said memory controller and responsive to said hit signal, for holding a bit indicating whether an instruction to be executed is provided by said cache memory or said main memory so that the accessible register indicates whether an instruction specified by said breakpoint address is provided by said cache memory or said main memory when control is transferred to the debugging routine.
Claim 3
Dependent Claim
227 words
A microcomputer, including a processor for processing data elements, said microcomputer comprising: a main memory for storing a plurality of data elements; a cache memory, coupled to said main memory, for storing a subset of the plurality of data elements stored in said main memory, where the processor specifies an address of a data element to be processed and processes a data element provided by said cache memory when the data element is included in said subset and processes a data element provided by said main memory otherwise; a memory controller, coupled to the cache, for issuing a hit signal indicating whether a data element to be processed is provided by said cache memory; a data break pointer, coupled to receive the address of a data element to be processed, for transferring control to a debugging routine when the address of a data element to be processed is a data breakpoint address held by said data break pointer; and a user-accessible register, coupled to said memory controller and responsive to said hit signal, for holding a bit indicating whether a data element to be processed is provided by said cache or said main memory so that the accessible register indicates whether a data element specified by said breakpoint address is provided by said cache memory or said main memory when control is transferred to the debugging routine.
Claim 4
Dependent Claim
227 words
A microcomputer, including a processor for processing data elements, said microcomputer comprising: a main memory for storing a plurality of data elements; a cache memory, coupled to said main memory, for storing a subset of the plurality of data elements stored in said main memory, where the processor specifies an address of a data element to be processed and processes a data element provided by said cache memory when the data element is included in said subset and processes a data element provided by said main memory otherwise; a memory controller, coupled to the cache, for issuing a hit signal indicating whether a data element to be processed is provided by said cache memory; a data break pointer, coupled to receive the address of a data element to be processed, for transferring control to a debugging routine when the address of a data element to be processed is a data breakpoint address held by said data break pointer; and a user-accessible register, coupled to said memory controller and responsive to said hit signal, for holding a bit indicating whether a data element to be processed is provided by said cache or said main memory so that the accessible register indicates whether a data element specified by said breakpoint address is provided by said cache memory or said main memory when control is transferred to the debugging routine.
Claim 5
Dependent Claim
78 words
A microcomputer according to claim 2 wherein said microcomputer further comprises: an access control unit for setting an access completion signal indicating that an instruction to be executed or data has not been provided to the processor in the shortest possible access time to indicate that a data element not been accessed from said cache memory; and wherein said user-accessible register holds a bit indicating whether an access completion signal has been set by said access control unit.
Claim 6
Dependent Claim
78 words
A microcomputer according to claim 3 wherein said access control unit includes a counter for counting a number of cycles requires to provide the processor with a data element to be processed, a comparison register for holding a preset value, and a comparator, coupled to said counter and said comparison register, for comparing said number counted by said counter with a preset value and setting said access completion signal when said number is greater than the preset value.
Claim 7
Dependent Claim
31 words
A microcomputer according to claim 1 or 2 wherein a plurality of said cache memories are provided and said user-accessible register holds a plurality of bits corresponding to the cache memories.
Claim 8
Dependent Claim
17 words
A microcomputer according to claim 1 or 2 wherein said cache memory is included in the microcomputer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-02-19 | 1999-08-21 | 2000-02-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-02-19 | 2003-08-21 | 2004-02-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-02-19 | 2007-08-21 | 2008-02-20 | $7700.00 | Window Closed / Lapsed |