US5218707A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit with remappable interrupt pins
Assignee: Dallas Semiconductor Corp
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Filing: 1988-10-28
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Granted: 1993-06-08
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Expires: 2008-10-28
Abstract
Abstract An integrated circuit wherein remapping logic permits the output-driver characteristics of a given pin to changed in software, by changing the data stored in a nonvolatile control bit.
Inventors
- 👤 Wendell L. Little
- 👤 Francis A. Scherpenberg
- 👤 Clark A. Williams
- 👤 William J. Podkowa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:50
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4063; G06F13/4068; G06F13/4072; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
157 words
An integrated circuit, comprising: a plurality of external interface contacts; internal circuit elements implementing a desired functionality, said functionality including the ability to generate interrupts for transmission to one or more other integrated circuits; a plurality of input buffers connected to receive electrical signals at ones of said external interface contacts, and to provide corresponding signals, on respective internal conductive lines, to respective ones of said internal circuit elements; a plurality of output buffers connected to receive electrical signals, on respective internal conductive lines, from respective ones of said internal circuit elements, and to provide, as corresponding outputs, electrical signals having predetermined electrical characteristics; and remapping logic, configured to selectably connect plural ones of said output buffers to plural ones of said internal conductive lines, in accordance with the value of one or more bits which are stored in nonvolatile memory, to provide a desired electrical configuration for output of said interrupt signals from the integrated circuit.
Claim 2
Dependent Claim
157 words
An integrated circuit, comprising: a plurality of external interface contacts; internal circuit elements implementing a desired functionality, said functionality including the ability to generate interrupts for transmission to one or more other integrated circuits; a plurality of input buffers connected to receive electrical signals at ones of said external interface contacts, and to provide corresponding signals, on respective internal conductive lines, to respective ones of said internal circuit elements; a plurality of output buffers connected to receive electrical signals, on respective internal conductive lines, from respective ones of said internal circuit elements, and to provide, as corresponding outputs, electrical signals having predetermined electrical characteristics; and remapping logic, configured to selectably connect plural ones of said output buffers to plural ones of said internal conductive lines, in accordance with the value of one or more bits which are stored in nonvolatile memory, to provide a desired electrical configuration for output of said interrupt signals from the integrated circuit.
Claim 3
Dependent Claim
27 words
The integrated circuit of claim 1, wherein some ones of said output buffers provide analog output signals, and others of said output buffers provide digital output signals.
Claim 4
Dependent Claim
34 words
The integrated circuit of claim 1, wherein some ones of said output buffers include bipolar driver transistors, and others of said output buffers include CMOS output drivers but do not include bipolar driver transistors.
Claim 5
Dependent Claim
23 words
The integrated circuit of claim 1, wherein said internal circuit elements implement a functionality which is complementary to the operation of a microprocessor.
Claim 6
Dependent Claim
52 words
The integrated circuit of claim 1, wherein at least one of said selectable output buffers is connected in parallel with a respective input buffer to provide a contact which can both send and receive signals, and at least one other of said selectable output buffers is connected to provide an output-only contact.
Claim 7
Dependent Claim
128 words
An integrated circuit, comprising: a plurality of external interface contacts; internal circuit elements implementing a desired functionality; a plurality of input buffers connected to receive electrical signals at ones of said external interface contacts, and to provide corresponding signals, on respective internal conductive lines, to respective ones of said internal circuit elements; a plurality of output buffers connected to receive electrical signals, on respective internal conductive lines, from respective ones of said internal circuit elements, and to provide, as corresponding outputs, electrical signals having predetermined electrical characteristics; and remapping logic, configured to selectably connect at least one of said output buffers to the selected one of a plurality of said internal conductive lines, in accordance with the value of one or more bits of data stored in memory.
Claim 8
Dependent Claim
128 words
An integrated circuit, comprising: a plurality of external interface contacts; internal circuit elements implementing a desired functionality; a plurality of input buffers connected to receive electrical signals at ones of said external interface contacts, and to provide corresponding signals, on respective internal conductive lines, to respective ones of said internal circuit elements; a plurality of output buffers connected to receive electrical signals, on respective internal conductive lines, from respective ones of said internal circuit elements, and to provide, as corresponding outputs, electrical signals having predetermined electrical characteristics; and remapping logic, configured to selectably connect at least one of said output buffers to the selected one of a plurality of said internal conductive lines, in accordance with the value of one or more bits of data stored in memory.
Claim 9
Dependent Claim
27 words
The integrated circuit of claim 6, wherein some ones of said output buffers provide analog output signals, and others of said output buffers provide digital output signals.
Claim 10
Dependent Claim
34 words
The integrated circuit of claim 6, wherein some ones of said output buffers include bipolar driver transistors, and others of said output buffers include CMOS output drivers but do not include bipolar driver transistors.
Claim 11
Dependent Claim
23 words
The integrated circuit of claim 6, wherein said internal circuit elements implement a functionality which is complementary to the operation of a microprocessor.
Claim 12
Dependent Claim
52 words
The integrated circuit of claim 6, wherein at least one of said selectable output buffers is connected in parallel with a respective input buffer to provide a contact which can both send and receive signals, and at least one other of said selectable output buffers is connected to provide an output-only contact.
Claim 13
Dependent Claim
124 words
An integrated circuit, comprising: a plurality of external interface contacts; internal circuit elements implementing a desired functionality; a plurality of input buffers connected to receive electrical signals at ones of said external interface contacts, and to provide corresponding signals, on respective internal conductive lines, to respective ones of said internal circuit elements; a plurality of output buffers connected to receive electrical signals, on respective internal conductive lines, from respective ones of said internal circuit elements, and to provide, as corresponding outputs, electrical signals having predetermined electrical characteristics; and remapping logic, configured to selectably connect plural ones of said buffers to plural ones of said internal conductive lines, in accordance with the value of one or more bits of data stored in nonvolatile battery-backed memory.
Claim 14
Dependent Claim
124 words
An integrated circuit, comprising: a plurality of external interface contacts; internal circuit elements implementing a desired functionality; a plurality of input buffers connected to receive electrical signals at ones of said external interface contacts, and to provide corresponding signals, on respective internal conductive lines, to respective ones of said internal circuit elements; a plurality of output buffers connected to receive electrical signals, on respective internal conductive lines, from respective ones of said internal circuit elements, and to provide, as corresponding outputs, electrical signals having predetermined electrical characteristics; and remapping logic, configured to selectably connect plural ones of said buffers to plural ones of said internal conductive lines, in accordance with the value of one or more bits of data stored in nonvolatile battery-backed memory.
Claim 15
Dependent Claim
27 words
The integrated circuit of claim 11, wherein some ones of said output buffers provide analog output signals, and others of said output buffers provide digital output signals.
Claim 16
Dependent Claim
27 words
The integrated circuit of claim 11, wherein some ones of said input buffers are configured to receive analog signals, and others are connected to receive digital signals.
Claim 17
Dependent Claim
34 words
The integrated circuit of claim 11, wherein some ones of said output buffers include bipolar driver transistors, and others of said output buffers include CMOS output drivers but do not include bipolar driver transistors.
Claim 18
Dependent Claim
23 words
The integrated circuit of claim 11, wherein said internal circuit elements implement a functionality which is complementary to the operation of a microprocessor.
Claim 19
Dependent Claim
66 words
The integrated circuit of claim 11, wherein said remapping logic is connected to selectably connect plural ones of said output buffers to ones of said internal conductive lines, and is also connected to selectably connect ones of said input buffers to plural ones of said internal conductive lines, all in accordance with the value of one or more bits of data stored in nonvolatile battery-backed memory.
Claim 20
Dependent Claim
52 words
The integrated circuit of claim 11, wherein at least one of said selectable output buffers is connected in parallel with a respective input buffer to provide a contact which can both send and receive signals, and at least one other of said selectable output buffers is connected to provide an output-only contact.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-06-07 | 1996-12-07 | 1997-06-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-06-07 | 2000-12-07 | 2001-06-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-06-07 | 2004-12-07 | 2005-06-08 | $7700.00 | Window Closed / Lapsed |