US5485029A — On-chip ground plane for semiconductor devices to…

Claim 1

Independent Claim 106 words

A semiconductor chip comprising: a substrate having a first conductivity type; a low resistivity semiconductor region in a plurality of non-device regions of the chip having a second conductivity type opposite said first conductivity type; reach-through low resistivity regions electrically connected to said low resistivity semiconductor region having said second conductivity type; and a front-side contact electrically connected to said reach-through regions for electrically coupling said reach-through regions and said low resistivity semiconductor region to a ground potential to electrically ground said low resistivity semiconductor region, wherein said low resistivity semiconductor region is formed concurrently with buried subcollector regions formed in device regions of the chip.

Claim 2

Dependent Claim 106 words

A semiconductor chip comprising: a substrate having a first conductivity type; a low resistivity semiconductor region in a plurality of non-device regions of the chip having a second conductivity type opposite said first conductivity type; reach-through low resistivity regions electrically connected to said low resistivity semiconductor region having said second conductivity type; and a front-side contact electrically connected to said reach-through regions for electrically coupling said reach-through regions and said low resistivity semiconductor region to a ground potential to electrically ground said low resistivity semiconductor region, wherein said low resistivity semiconductor region is formed concurrently with buried subcollector regions formed in device regions of the chip.

Claim 3

Dependent Claim 27 words

The semiconductor chip according to claim 1, wherein said buried subcollector regions and said low resistivity semiconductor region are doped n + and are on said substrate.

Claim 4

Dependent Claim 27 words

The semiconductor chip according to claim 1, wherein said buried subcollector regions and said low resistivity semiconductor region are doped p + and are on said substrate.

Claim 5

Dependent Claim 26 words

The semiconductor chip according to claim 1, wherein said chip is formed in bulk silicon, and wherein said low resistivity semiconductor region is a buried region.

Claim 6

Dependent Claim 15 words

The semiconductor chip of claim 1 having device regions in which bipolar transistors are formed.

Claim 7

Dependent Claim 16 words

The semiconductor chip of claim 1 having device regions in which thin film transistors are formed.

Claim 8

Dependent Claim 75 words

A semiconductor chip comprising: a plurality of devices in trench isolation regions of the chip; a plurality of non-device regions outside of said trench isolation regions; buried low resistivity semiconductor regions within a plurality of said non-device regions; reach-through regions electrically connected to said buried low resistivity semiconductor regions; and top-side contacts to electrically connect said reach-through regions and said low resistivity semiconductor regions to a ground potential to thereby provide an on-chip ground plane.

Claim 9

Dependent Claim 75 words

A semiconductor chip comprising: a plurality of devices in trench isolation regions of the chip; a plurality of non-device regions outside of said trench isolation regions; buried low resistivity semiconductor regions within a plurality of said non-device regions; reach-through regions electrically connected to said buried low resistivity semiconductor regions; and top-side contacts to electrically connect said reach-through regions and said low resistivity semiconductor regions to a ground potential to thereby provide an on-chip ground plane.

Claim 10

Dependent Claim 51 words

The semiconductor chip according to claim 7, wherein at least one of said plurality of devices comprise bipolar transistors having buried subcollector regions; and wherein said buried subcollector regions and said buried low resistivity semiconductor regions comprise a single concurrently-formed semiconductor layer, but are electrically isolated by said trench isolation regions.

Claim 11

Dependent Claim 26 words

The semiconductor chip according to claim 8, wherein said buried subcollector regions and said buried low resistivity semiconductor regions are further electrically isolated by P-N junctions.

Claim 12

Dependent Claim 38 words

The semiconductor chip according to claim 8, wherein said chip includes a p - type substrate; and wherein said buried subcollector regions and said buried low resistivity semiconductor regions are doped n + and are on said substrate.

Claim 13

Dependent Claim 38 words

The semiconductor chip according to claim 8, wherein said chip includes a n - type substrate; and wherein said buried subcollector regions and said buried low resistivity semiconductor regions are doped p + and are on said substrate.

Claim 14

Dependent Claim 35 words

The semiconductor chip according to claim 8, wherein said chip includes a substrate; and wherein said buried subcollector regions and said buried low resistivity semiconductor regions are doped n + and are on said substrate.

Claim 15

Dependent Claim 35 words

The semiconductor chip according to claim 8, wherein said chip includes a substrate; and wherein said buried subcollector regions and said buried low resistivity semiconductor regions are doped p + and are on said substrate.

Claim 16

Independent Claim 83 words

A method for providing an on-chip ground plane for a semiconductor chip, the method comprising the steps of: forming a plurality of device regions and a plurality of non-device regions on a substrate, wherein said device regions are coplanar with and laterally isolated from said non-device regions; providing high dopant concentration semiconductor regions in a substantial number of said plurality of non-device regions; and electrically connecting said high dopant concentration semiconductor regions to a ground potential to thereby provide the on-chip ground plane.

Claim 17

Independent Claim 83 words

A method for providing an on-chip ground plane for a semiconductor chip, the method comprising the steps of: forming a plurality of device regions and a plurality of non-device regions on a substrate, wherein said device regions are coplanar with and laterally isolated from said non-device regions; providing high dopant concentration semiconductor regions in a substantial number of said plurality of non-device regions; and electrically connecting said high dopant concentration semiconductor regions to a ground potential to thereby provide the on-chip ground plane.

Claim 18

Dependent Claim 34 words

The method of claim 14 wherein the chip is formed on a silicon on insulator substrate having a thin silicon film, and wherein said high dopant concentration semiconductor regions are portions of said film.

Claim 19

Dependent Claim 23 words

The method of claim 14 further comprising the step of forming one of field effect transistors and bipolar transistors in said device regions.

Claim 20

Independent Claim 73 words

A method for providing an on-chip ground plane for a semiconductor chip having a plurality of devices in trench isolation regions and non-device regions outside of the trench isolation regions, comprising the steps of: providing buried high dopant concentration semiconductor regions within a substantial number of the non-device regions of the chip; and electrically connecting said buried high dopant concentration semiconductor regions to a ground potential to thereby provide the on-chip ground plane.

Claim 21

Independent Claim 73 words

A method for providing an on-chip ground plane for a semiconductor chip having a plurality of devices in trench isolation regions and non-device regions outside of the trench isolation regions, comprising the steps of: providing buried high dopant concentration semiconductor regions within a substantial number of the non-device regions of the chip; and electrically connecting said buried high dopant concentration semiconductor regions to a ground potential to thereby provide the on-chip ground plane.

Claim 22

Dependent Claim 55 words

A semiconductor chip comprising: a semiconductor device region formed on an insulating substrate; a low resistivity semiconductor non-device region coplanar with, and laterally isolated from, said device region; a front-side contact electrically connected to said non-device region for electrically coupling said non-device region to a ground potential so as to form an on-chip ground plane.

Claim 23

Dependent Claim 55 words

A semiconductor chip comprising: a semiconductor device region formed on an insulating substrate; a low resistivity semiconductor non-device region coplanar with, and laterally isolated from, said device region; a front-side contact electrically connected to said non-device region for electrically coupling said non-device region to a ground potential so as to form an on-chip ground plane.

Claim 24

Dependent Claim 16 words

The semiconductor chip according to claim 18, wherein said device region comprises a field effect transistor.

Claim 25

Dependent Claim 69 words

A semiconductor chip comprising: a semiconductor device region formed on a substrate having a first conductivity type; a low resistivity semiconductor non-device region coplanar with, and laterally isolated from, said device region, and having a conductivity type opposite said first conductivity type; a front-side contact electrically connected to said non-device region for electrically coupling said non-device region to a ground potential so as to form an on-chip ground plane.

Claim 26

Dependent Claim 69 words

A semiconductor chip comprising: a semiconductor device region formed on a substrate having a first conductivity type; a low resistivity semiconductor non-device region coplanar with, and laterally isolated from, said device region, and having a conductivity type opposite said first conductivity type; a front-side contact electrically connected to said non-device region for electrically coupling said non-device region to a ground potential so as to form an on-chip ground plane.

Claim 27

Dependent Claim 31 words

The semiconductor chip according to claim 20, wherein said device region comprises a buried subcollector region, and wherein said buried subcollector region and said non-device region are doped p + .

Claim 28

Dependent Claim 31 words

The semiconductor chip according to claim 20, wherein said device region comprises a buried subcollector region, and wherein said buried subcollector region and said non-device region are doped n + .

Claim 29

Dependent Claim 14 words

The semiconductor chip of claim 20 wherein said device region comprises a bipolar transistor.

Claim 30

Dependent Claim 15 words

The semiconductor chip of claim 20 wherein said device region comprises a thin film transistor.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1999-01-15	1999-07-17	2000-01-16	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2003-01-15	2003-07-17	2004-01-16	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2007-01-15	2007-07-17	2008-01-16	$7700.00	Window Closed / Lapsed

On-chip ground plane for semiconductor devices to reduce parasitic signal propagation

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