Semiconductor integrated circuit containing analogous and digital components

Claim 2

A semiconductor integrated circuit in which an analog circuit and a digital circuit are formed on a single chip, characterized by comprising: a first semiconductor region (11) containing an impurity of a first conductivity type (P); a first high impurity semiconductor region (12) formed on said first semiconductor region (11) and containing an impurity of a second conductivity type (N) at a high concentration; a second semiconductor region (13) formed on said first high impurity semiconductor region (12) and con­taining the impurity of the second conductivity type (N); a first isolation portion (19) extending through said second semiconductor region (13) and said first high impurity semiconductor region (12) and reaching said first semiconductor region (11), for isolating adjacent transistors in an analog circuit (27) formed in said second semiconductor region (13); and a second isolation portion (17) formed in said second semiconductor region (13) and isolating adjacent transistors formed in a digital circuit (28) formed on said second semiconductor region (13).

Claim 3

A circuit according to claim 1, characterized in that a first high-impurity region (14A) of the second conductivity type is formed in said analog circuit (27), so as to extend through said second semiconductor region (13) and reach said first high-impurity semiconductor region (12), and a second high-impurity region (14B) of the second conductivity type is formed in said digital circuit (28), so as to extend through said second high-­impurity semiconductor region (13) and reach said first high impurity semiconductor region (12).

Claim 4

A circuit according to claim 1, characterized in that a second high impurity semiconductor region (23) is formed in said first semiconductor region (11), at the bottom of said first isolation portion (19), and contains said impurity of the first conductivity type (P) at a high concentration.

Claim 5

A circuit according to claim 1, characterized in that the bottom of said second isolation portion (12) reaches a boundary between said first high impurity semiconductor region (12) and said second semiconductor region (13).

Claim 6

A circuit according to claim 1, characterized in that said first isolation portion (19) comprises a first trench vertically formed in said first semicon­ductor region (11), said first high impurity semicon­ductor region (12), and said second semiconductor region (13), an insulating film (24) formed on a wall surface of said first trench, and a polysilicon layer (25) buried in a wall surface of said insulating film (24).

Claim 7

A circuit according to claim 1, characterized in that said second isolation portion (17) comprises a second trench (17) vertically formed in said second semiconductor region (13), an insulating film (24) formed on a wall surface of said second trench (17), and a polysilicon layer (25) buried in a wall surface of said insulating film (24).

Claim 8

A semiconductor integrated circuit in which an analog circuit and a digital circuit are formed on a single chip, characterized by comprising: a first semiconductor region (11), containing an impurity of a first conductivity type; a first high-impurity semiconductor region (12a) formed on part of said first semiconductor region (11) and containing an impurity of a second conductivity type at a high concentration; a second semiconductor region (72), formed on said first high-impurity semiconductor region (12a) and containing said impurity of the second conductivity type; a third semiconductor region (73), formed on said first semiconductor region (11), adjacent to said second semiconductor region (72), and containing said impurity of the first conductivity type; a first isolation portion (19), extending through said second semiconductor region (72) and said first high-impurity semiconductor region (12a), and reaching said first semiconductor region (11), for isolating adjacent transistors in said analog circuit (27) formed in said second semiconductor region (72); and a second isolation portion (17), for isolating adjacent transistors in said digital circuit (28) formed on said second semiconductor region (72) and said third semiconductor region (73).

Claim 9

A semiconductor integrated circuit in which an analog circuit and a digital circuit are formed on a single chip, characterized by comprising: a first semiconductor region (11), containing an impurity of a first conductivity type; a first high-impurity semiconductor region (12a) formed on part of said first semiconductor region (11) and containing an impurity of a second conductivity type at a high concentration; a second semiconductor region (72), formed on said first high-impurity semiconductor region (12a) and containing said impurity of the second conductivity type; a third semiconductor region (73), formed on said first semiconductor region (11), adjacent to said second semiconductor region (72), and containing said impurity of the first conductivity type; a first isolation portion (19), extending through said second semiconductor region (72) and said first high-impurity semiconductor region (12a), and reaching said first semiconductor region (11), for isolating adjacent transistors in said analog circuit (27) formed in said second semiconductor region (72); and a second isolation portion (17), for isolating adjacent transistors in said digital circuit (28) formed on said second semiconductor region (72) and said third semiconductor region (73).

Claim 10

A circuit according to claim 7, characterized in that a second high impurity semiconductor region (23) is formed in said first semiconductor region (11), at the bottom of said first isolation portion (19), and contains said impurity of the first conductivity type at a high concentration.

Claim 11

A circuit according to claim 7, characterized in that the bottom of said second isolation portion (17) reaches a boundary between said first high impurity semiconductor region (12a) and said second semiconductor region (72).

Claim 12

A circuit according to claim 7, characterized in that said first isolation portion (19) comprises a first trench, vertically formed in said first semi­conductor region (11), said first high impurity semi­conductor region (12a), and said second semiconductor region (72), an isulating film (24) formed on a wall surface of said first trench, and a polysilicon layer (25) buried in a wall surface of said insulating film (24).

Claim 13

A circuit according to claim 7, characterized in that said second isolation portion (17) comprises a second trench, vertically formed in said second semiconductor region (72), and said fourth semiconductor region (73), an insulating film (24) formed on a wall surface of said second trench, and a polysilicon layer (25) buried in a wall surface of said insulating film (24).