Phase error processor circuit with a comparator input swapping technique

Claim 2

A phase-locked loop apparatus for generating a local clock signal having a frequency and phase equal to the frequency and phase of a data stream incoming to said phase-locked loop, said apparatus comprising; an oscillator for generating said local clock signal, said signal having a phase and a frequency, a phase detector coupled to receive said local clock signal and said incoming data stream and generate a first pulse train having pulses of a duration proportional to the phase difference between said local clock signal and said incoming data stream and a second pulse train having reference pulses of a duration equal to the duration of said pulses of said first pulse train when there is no phase difference between said incoming data stream and said local clock signal, and a phase error processor comprising, a first integrator having an input terminal and an output terminal, a second integrator having an input terminal and an output terminal, a comparator having a first input terminal coupled to said output terminal of said first integrator and a second input terminal coupled to said output terminal of said second integrator, and an output terminal for outputting a phase error direction signal, said oscillator being responsive to said phase error direction signal to advance or retard said phase of said local clock signal, a switch having first and second conditions, said switch coupled to receive said first and second pulse trains and provide said first pulse train to said first integrator and said second pulse train to said second integrator when in said first condition and provide said second pulse train to said first integrator and said first pulse train to said second integrator when in said second condition, and control means for alternately placing said switch in said first and second conditions at predetermined equal intervals.

Claim 3

An apparatus as set forth in claim 1 wherein said control means comprises a finite state machine which generates a SWAP signal which switches between first and second states at said regular intervals, said SWAP signal coupled to a control input terminal of said switch to cause said switch to be in said first condition responsive to said SWAP signal being in said first state and to be in said second condition responsive to said SWAP signal being in said second state.

Claim 4

An apparatus as set forth in claim 2 further comprising an exclusive-OR gate having a first input terminal coupled to receive said phase error direction signal and a second input terminal coupled to said SWAP signal and an output terminal, said oscillator being controlled by said output signal of said exclusive-OR gate.

Claim 5

An apparatus as set forth in claim 3 further comprising a D flip flop having a data input terminal coupled to said output terminal of said exclusive-OR gate, said D flip flop being controlled to latch a signal at its data input terminal once per interval and having a data output terminal coupled to said oscillator for outputting an UP/DOWN signal, said oscillator being controlled by said UP/DOWN signal to advance the phase of said local clock when in a first state and to retard the phase of said local clock signal when in a second state.

Claim 6

An apparatus as set forth in claim 4 further comprising a phase error gating circuit coupled between said phase detector and said switch for receiving said first and second pulse trains and providing a predetermined number of pulses on each of said pulse trains to said switch per each of said predetermined intervals.

Claim 7

An apparatus as set forth in claim 5 wherein said predetermined number is two.

Claim 8

An apparatus as set forth in claim 6 wherein said control means further generates a STROBE signal which is asserted once per each of said intervals, said D flip flop being controlled to latch said signal at its data input terminal responsive to said assertion of said STROBE signal.

Claim 9

An apparatus as set forth in claim 7 wherein said control means further generates a DUMP signal which is coupled to said first and second integrators and is asserted once per each of said intervals after said STROBE signal is asserted, said first and second integrators being responsive to said DUMP signal to reset to a zero state.

Claim 10

An apparatus as set forth in claim 8 further comprising a digital loop filter coupled between said phase error processor and said oscillator.

Claim 11

A phase error processing circuit for generating a signal indicating whether a phase of a first input signal lags or leads the phase of a second input signal, said circuit comprising; a first integrator having an input terminal and an output terminal, a second integrator having an input terminal and an output terminal, a comparator having a first input terminal coupled to said output terminal of said first integrator and a second input terminal coupled to said output terminal of said second integrator, and an output terminal for outputting a phase error direction signal, a switch having first and second conditions, said switch coupled to receive first and second pulse trains and provide said first pulse train to said first integrator and said second pulse train to said second integrator when in said first condition and provide said second pulse train to said first integrator and said first pulse train to said second integrator when in said second condition, said first pulse train having pulses of a duration proportional to the phase difference between said first and second input signals and said second pulse train having reference pulses of a duration equal to the duration of said pulses of said first pulse train when there is no phase difference between said first and second input signals, and control means for alternately placing said switch in said first and second conditions at predetermined equal intervals.

Claim 12

A phase error processing circuit for generating a signal indicating whether a phase of a first input signal lags or leads the phase of a second input signal, said circuit comprising; a first integrator having an input terminal and an output terminal, a second integrator having an input terminal and an output terminal, a comparator having a first input terminal coupled to said output terminal of said first integrator and a second input terminal coupled to said output terminal of said second integrator, and an output terminal for outputting a phase error direction signal, a switch having first and second conditions, said switch coupled to receive first and second pulse trains and provide said first pulse train to said first integrator and said second pulse train to said second integrator when in said first condition and provide said second pulse train to said first integrator and said first pulse train to said second integrator when in said second condition, said first pulse train having pulses of a duration proportional to the phase difference between said first and second input signals and said second pulse train having reference pulses of a duration equal to the duration of said pulses of said first pulse train when there is no phase difference between said first and second input signals, and control means for alternately placing said switch in said first and second conditions at predetermined equal intervals.

Claim 13

A circuit as set forth in claim 10 wherein said control means comprises a finite state machine which generates a SWAP signal which switches between first and second states at said predetermined intervals, said SWAP signal coupled to a control input terminal of said switch to cause said switch to be in said first condition responsive to said SWAP signal being in said first state and to be in said second condition responsive to said SWAP signal being in said second state.

Claim 14

A circuit as set forth in claim 11 further comprising an exclusive-OR gate having a first input terminal coupled to receive said phase error direction signal and a second input terminal coupled to said SWAP signal and an output terminal so as to invert said output of said comparator in alternate ones of said predetermined intervals.

Claim 15

An apparatus as set forth in claim 12 further comprising a D flip flop having a data input terminal coupled to said output terminal of said exclusive-OR gate, said D flip flop being controlled to latch a signal at its data input terminal once per predetermined interval and having a data output terminal for outputting an UP/DOWN signal.

Claim 16

An apparatus as set forth in claim 13 further comprising a phase error gating circuit coupled before said switch for receiving said first and second pulse trains and providing a predetermined number of pulses on each of said pulse trains to said switch per each of said predetermined intervals.

Claim 17

An apparatus as set forth in claim 14 wherein said predetermined number is two.

Claim 18

An apparatus as set forth in claim 15 wherein said control means further generates a STROBE signal which is asserted once per each of said intervals, said D flip flop being controlled to latch said signal at its data input terminal responsive to said assertion of said STROBE signal.

Claim 19

An apparatus as set forth in claim 16 wherein said control means further generates a DUMP signal which is coupled to said first and second integrators and is asserted once per each of said intervals after said STROBE signal is asserted, said first and second integrators being responsive to said DUMP signal to reset to a zero state.

Claim 20

A phase-locked loop apparatus for generating a local clock signal having a frequency and phase equal to the frequency and phase of a data stream incoming to said phase-locked loop, said apparatus comprising; an oscillator for generating said local clock signal, said signal having a phase and a frequency, a phase detector coupled to receive said local clock signal and said incoming data stream and generate a first pulse train having pulses of a duration proportional to the phase difference between said local clock signal and said incoming data stream and a second pulse train having reference pulses of a duration equal to the pulse width of said pulses of said first pulse train when there is no phase difference between said incoming data stream and said local clock signal, and a phase error processor comprising, a first integrator having an input terminal and an output terminal, a second integrator having an input terminal and an output terminal, a comparator having a first input terminal coupled to said output terminal of said first integrator and a second input terminal coupled to said output terminal of said second integrator, and an output terminal for outputting a phase error direction signal, said oscillator being responsive to said phase error direction signal to advance or retard said phase of said local clock signal, a switch having first and second conditions, said switch coupled to receive said first and second pulse trains and provide said first pulse train to said first integrator and said second pulse train to said second integrator when in said first condition and provide said second pulse train to said first integrator and said first pulse train to said second integrator when in said second condition, an exclusive-OR gate having a first input terminal coupled to receive said phase error direction signal and a second input terminal and an output terminal, said oscillator being controlled by said output signal of said exclusive-OR gate, a D flip flop having a data input terminal coupled to said output terminal of said exclusive-OR gate, and having a data output terminal coupled to said oscillator for outputting an UP/DOWN signal, said oscillator being controlled by said UP/DOWN signal to advance the phase of said local clock when in a first state and to retard the phase of said local clock signal when in a second state, a finite state machine which generates a SWAP signal which switches between first and second states at said predetermined intervals, said SWAP signal coupled to a control input terminal of said switch to cause said switch to be in said first condition responsive to said SWAP signal being in said first state and to be in said second condition responsive to said SWAP signal being in said second state and further coupled to said second input terminal of said exclusive-OR gate to cause said exclusive-OR gate to invert said phase error direction signal when in said first state and to pass said phase error direction signal when in said second state, said finite state machine further generating a STROBE signal which is asserted once per each of said intervals, said D flip flop being controlled to latch said signal at its data input terminal responsive to said assertion of said STROBE signal and a DUMP signal which is coupled to said first and second integrators and is asserted once per each of said intervals after said STROBE signal is asserted, said first and second integrators being responsive to said DUMP signal to reset to a zero state, and a digital loop filter coupled between said phase error processor and said oscillator.

Claim 21

A phase-locked loop apparatus for generating a local clock signal having a frequency and phase equal to the frequency and phase of a data stream incoming to said phase-locked loop, said apparatus comprising; an oscillator for generating said local clock signal, said signal having a phase and a frequency, a phase detector coupled to receive said local clock signal and said incoming data stream and generate a first pulse train having pulses of a duration proportional to the phase difference between said local clock signal and said incoming data stream and a second pulse train having reference pulses of a duration equal to the pulse width of said pulses of said first pulse train when there is no phase difference between said incoming data stream and said local clock signal, and a phase error processor comprising, a first integrator having an input terminal and an output terminal, a second integrator having an input terminal and an output terminal, a comparator having a first input terminal coupled to said output terminal of said first integrator and a second input terminal coupled to said output terminal of said second integrator, and an output terminal for outputting a phase error direction signal, said oscillator being responsive to said phase error direction signal to advance or retard said phase of said local clock signal, a switch having first and second conditions, said switch coupled to receive said first and second pulse trains and provide said first pulse train to said first integrator and said second pulse train to said second integrator when in said first condition and provide said second pulse train to said first integrator and said first pulse train to said second integrator when in said second condition, an exclusive-OR gate having a first input terminal coupled to receive said phase error direction signal and a second input terminal and an output terminal, said oscillator being controlled by said output signal of said exclusive-OR gate, a D flip flop having a data input terminal coupled to said output terminal of said exclusive-OR gate, and having a data output terminal coupled to said oscillator for outputting an UP/DOWN signal, said oscillator being controlled by said UP/DOWN signal to advance the phase of said local clock when in a first state and to retard the phase of said local clock signal when in a second state, a finite state machine which generates a SWAP signal which switches between first and second states at said predetermined intervals, said SWAP signal coupled to a control input terminal of said switch to cause said switch to be in said first condition responsive to said SWAP signal being in said first state and to be in said second condition responsive to said SWAP signal being in said second state and further coupled to said second input terminal of said exclusive-OR gate to cause said exclusive-OR gate to invert said phase error direction signal when in said first state and to pass said phase error direction signal when in said second state, said finite state machine further generating a STROBE signal which is asserted once per each of said intervals, said D flip flop being controlled to latch said signal at its data input terminal responsive to said assertion of said STROBE signal and a DUMP signal which is coupled to said first and second integrators and is asserted once per each of said intervals after said STROBE signal is asserted, said first and second integrators being responsive to said DUMP signal to reset to a zero state, and a digital loop filter coupled between said phase error processor and said oscillator.

Claim 22

An apparatus as set forth in claim 18 further comprising a phase error gating circuit coupled between said phase detector and said switch for receiving said first and second pulse trains and providing a predetermined number of pulses on each of said pulse trains to said switch per each of said predetermined intervals.

Claim 25

A method as set forth in claim 20 wherein said first and second time windows each comprise a plurality of time windows, said first and second time windows being interleaved such that said first and second integrators alternately integrate said first second pulse trains during alternate windows.

Claim 26

A method as set forth in claim 21 wherein step (6) comprises the steps of; (6.1) comparing the output of said first integrator with the output of said second integrator and generating a compare signal which is in a first state if the output of said first integrator is greater than the output of said second integrator and is in a second condition if the output of said first integrator is less than the output of said second integrator, and (6.2) inverting the compare signal during said second time windows.

Claim 27

A method as set forth in claim 22 wherein step (6) further comprises the step of; (6.3) latching the inverted compare signal once per window at an instant after the first pulses and the reference pulses associated with that window have occurred to generate said control signal.

Claim 28

A method as set forth in claim 20 wherein step (5) comprises the step of; (5.1) providing said first and second pulse trains each to a switch, and (5.2) alternately switching said switches so as to couple said first pulse train to said first integrator and said second pulse train to said second integrator during said first time windows and to couple said first pulse train to said second integrator and said second pulse train to said first integrator during said second time windows.

Claim 29

A method as set forth in claim 20 further comprising the step of; (2.5) providing only a predetermined number of pulses on said pulse trains to said switches during each of said time windows.

Claim 30

A method as set forth in claim 25 wherein said predetermined number is two.

Claim 31

A method as set forth in claim 20 further comprising the step of; (8) discharging said integrators each window after said inverted comparator output signal is latched.