US5337335A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Phase locked loop with frequency deviation detector and decoder circuit comprising such a phase locked loop
Assignee: US Philips Corp
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Filing: 1992-11-23
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Granted: 1994-08-09
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Expires: 2012-11-23
Abstract
Abstract A phase locked loop includes a capture aid circuit to pull the frequency of the oscillator towards the bit frequency of a data signal HF in consisting of pulses of variable lengths, each length being an integral multiple of a single bit basic length unit. The capture aid circuit includes a pulse length detector for measuring and rounding pulse length to the nearest integral number of basic length units, and determining the difference (ΔRL) between the measured and rounded length value (RL). For small frequency deviations the rounding error (ΔRL) signal is used as a frequency deviation control signal for increasing or decreasing the oscillator frequency. For larger frequency deviations the minimum pulse length will be either more or less than a predetermined number of length units. That is detected by supplying the rounded pulse length signal (RL) signal to a pulse length decoder which determines the presence of pulses having a minimum length below the predetermined number of units or the absence of pulses having such minimum length. From signals indicative of those conditions further control signals are derived in a frequency deviation detector, which further control signals adjust the oscillator frequency so as to bring the frequency deviation within the range in which the rounding error (ΔRL) signal can be used to precisely adjust the oscillator frequency to the bit frequency of the data signal.
Inventors
- 👤 Henri Cloetens
- 👤 Robertus W. C. Groen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 18:33
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/10; H03L7/113
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
345 words
A phase lock loop for locking a local digital oscillator in said loop to a clock frequency determined by a received data signal consisting of pulses of variable lengths, the length of each pulse being an integral multiple of a basic length unit corresponding to said clock frequency; said phase lock loop comprising: a phase detector having an oscillator input for receiving the digital oscillator signal and a data input for receiving the data signal, said phase detector producing at an output thereof a phase difference signal (Δφ) indicative of a phase difference between the pulses in said oscillator signal and the pulses in said data signal; a digital loopfilter for receiving said phase difference signal (Δφ) and having an output coupled to a control input of said oscillator; a frequency capture circuit having a first input coupled to said oscillator to receive said oscillator signal, a second input coupled to the output of said phase detector to receive said phase difference signal (Δφ), and a third input coupled to the data input of said phase detector to receive said data signal; said frequency capture circuit detecting a difference in frequency between said data signal and said oscillator signal and to produce a frequency deviation signal at an output thereof, said output being coupled to a control input of said loopfilter to supply said frequency deviation signal thereto, said frequency deviation signal causing said loopfilter to produce at its output a frequency control signal for controlling the frequency of said oscillator; and a pulse length detector circuit comprised in said frequency capture circuit for measuring the length of a pulse in said data signal and rounding it to the nearest integral number of periods of said oscillator signal, said pulse length detector circuit producing a pulse length signal (RL) indicative of the rounded length and a length deviation signal (ΔRL) indicative of deviation between said rounded length and the measured length; said frequency capture circuit deriving said frequency deviation signal on the basis of said rounded length signal (RL) and said length deviation signal (ΔRL).
Claim 2
Dependent Claim
345 words
A phase lock loop for locking a local digital oscillator in said loop to a clock frequency determined by a received data signal consisting of pulses of variable lengths, the length of each pulse being an integral multiple of a basic length unit corresponding to said clock frequency; said phase lock loop comprising: a phase detector having an oscillator input for receiving the digital oscillator signal and a data input for receiving the data signal, said phase detector producing at an output thereof a phase difference signal (Δφ) indicative of a phase difference between the pulses in said oscillator signal and the pulses in said data signal; a digital loopfilter for receiving said phase difference signal (Δφ) and having an output coupled to a control input of said oscillator; a frequency capture circuit having a first input coupled to said oscillator to receive said oscillator signal, a second input coupled to the output of said phase detector to receive said phase difference signal (Δφ), and a third input coupled to the data input of said phase detector to receive said data signal; said frequency capture circuit detecting a difference in frequency between said data signal and said oscillator signal and to produce a frequency deviation signal at an output thereof, said output being coupled to a control input of said loopfilter to supply said frequency deviation signal thereto, said frequency deviation signal causing said loopfilter to produce at its output a frequency control signal for controlling the frequency of said oscillator; and a pulse length detector circuit comprised in said frequency capture circuit for measuring the length of a pulse in said data signal and rounding it to the nearest integral number of periods of said oscillator signal, said pulse length detector circuit producing a pulse length signal (RL) indicative of the rounded length and a length deviation signal (ΔRL) indicative of deviation between said rounded length and the measured length; said frequency capture circuit deriving said frequency deviation signal on the basis of said rounded length signal (RL) and said length deviation signal (ΔRL).
Claim 3
Dependent Claim
45 words
A phase lock loop as claimed in claim 1, wherein said pulse length detector circuit determines whether to round the measured length of a pulse in said data signal to a next higher or a next lower integral number of periods of said oscillator signal.
Claim 4
Dependent Claim
50 words
A phase lock loop as claimed in claim 2, wherein said frequency capture circuit further comprises means for inhibiting the length deviation signal (ΔRL) when it has derived by said pulse length detector circuit from a data pulse having a rounded length which deviates from a predetermined rounded length value.
Claim 5
Dependent Claim
40 words
A phase lock loop as claimed in claim 1, wherein said pulse length detector circuit selects for length measurement those pulses in said data signal which are shortest in respect of the number of consecutive basic length units included therein.
Claim 6
Dependent Claim
75 words
A phase lock loop as claimed in claim 4, wherein said frequency capture circuit further comprises a frequency deviation detector circuit for generating at the output of said frequency capture circuit a frequency control signal for said local oscillator, said frequency control signal having a first value when the shortest detected pulse length is below a predetermined minimum length and having a second value when the shortest detected pulse length exceeds said predetermined minimum length.
Claim 7
Dependent Claim
40 words
A phase lock loop as claimed in claim 1, wherein said pulse length detector circuit selects for length measurement those pulses in said data signal which are longest in respect of the number of consecutive basic length units included therein.
Claim 8
Dependent Claim
76 words
A phase lock loop as claimed in claim 6, wherein said frequency capture circuit further comprises a frequency deviation detector circuit for generating at the output of said frequency capture circuit a frequency control signal for said local oscillator, said frequency control signal having a first value when the longest detected pulse length is above a predetermined maximum length and having a second value when the longest detected pulse length is below said predetermined maximum length.
Claim 9
Dependent Claim
43 words
A phase lock loop as claimed in claim 1, wherein the frequency capture circuit further comprises a frequency lock detector for detecting whether characteristic pulse sequences in the data signal recur at predetermined periodic distances with respect to periods of the oscillator signal.
Claim 10
Dependent Claim
36 words
A phase lock loop as claimed in claim 8, wherein said frequency lock detector deactivates the frequency deviation signals produced by the frequency capture circuit when said characteristic pulse sequences recur at said predetermined periodic distances.
Claim 11
Dependent Claim
176 words
A phase lock loop as claimed in claim 8, wherein said frequency capture circuit further comprises: a pulse length decoder circuit having an input coupled to said pulse length detector circuit to receive said pulse length signal (RL) therefrom; and a frequency deviation detector circuit having inputs coupled to outputs of said pulse length decoder circuit, said frequency deviation detector circuit having an output from which it supplies frequency control signals at the output of said frequency capture circuit; said frequency lock detector producing at a control output thereof a control signal which is in a first state when the measured distance between said characteristic pulse sequences falls outside a predetermined window and which is in a second state when said measured distance falls inside said window, said control output controlling switching means coupled to said pulse length decoder circuit and to said frequency deviation detector circuit for selecting between the outputs of said circuits depending on whether the control signal produced by said frequency lock detector is in the first or the second state thereof.
Claim 12
Dependent Claim
19 words
The phase locked loop according to claim 4, wherein said phase lock loop is integrated into an integrated circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-08 | 1998-02-07 | 1998-08-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-08 | 2002-02-07 | 2002-08-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-08 | 2006-02-07 | 2006-08-09 | $7700.00 | Window Closed / Lapsed |