Phase-locked loop with sync detector

Claim 2

A phase-locked loop comprising: phase detector means for receiving a PLL input pulse signal frequency f 0 and for receiving a PLL output pulse signal of said phase-locked loop, said PLL input and output pulse signals being applied to said phase detector means for producing a control signal representative of a difference in frequency or phase between said PLL input and output pulse signals; a variable-frequency oscillator for generating VFO output pulses having a fixed frequency N×f 0 when said control signal indicates absence of said frequency or phase difference between said PLL input and output pulse signals, first VFO output pulses having a variable frequency when said control signal indicates presence of said frequency or phase difference, where N is equal to or greater than 4; a first frequency divider for dividing the frequency of said VFO output pulses by N for generating first frequency-divided pulses as said PLL output pulse signal; a second frequency divider for dividing the frequency of said PLL input pulse signal by an integer M equal to or greater than 2 to produce second frequency-divided pulses at 1/M of the frequency of the PLL input pulse signal; and sync detection means responsive to said VFO output pulses and said second frequency-divided pulses for detecting when the number of said VFO output pulses during an interval between successive pulses generated by the second frequency divider is substantially equal to M×N, and in response thereto, generating a signal indicating that a phase alignment is established between said PLL input and output pulse signals.

Claim 3

A phase-locked loop as claimed in claim 1, wherein the sync detection means comprises: a counter for counting the pulses generated by the variable frequency oscillator and providing a count value representative of the number of counted pulses; detector means for detecting when said count value is equal to (M×N)-1 and in response thereto, generating said phase-alignment indicating signal; and means for resetting the counter to zero in response to each of the pulses generated by the second frequency divider.

Claim 4

A phase-locked loop with a sync detection circuit as claimed in claim 2, wherein said sync detection means includes a flip-flop for assuming one of the binary states of an output of said detector means in response to each pulse of the frequency-divided input pulse signal supplied from said second frequency divider.

Claim 5

A phase-locked loop comprising: phase detector means for receiving a PLL input pulse signal at frequency f 0 and for receiving a PLL output pulse signal of said phase-locked loop, said PLL input and output pulse signals being applied to said phase detector means for producing a control signal representative of a phase difference between said PLL input and output pulse signals; variable-frequency oscillator means responsive to said control signal for generating VFO output pulses having a frequency which is variable in accordance with said phase difference; frequency divider means for dividing the frequency of said VFO output pulses by N for generating said PLL output pulse signal, where N is an integer equal to or greater than 2; sync detection means for receiving said PLL input pulse signal and said VFO output pulses and detecting when M×N pulses are generated by said oscillator means during an interval in which M input pulses are received as said PLL input pulse signal, and in response thereto, generating an output signal indicating that a phase alignment is established between said PLL input and output pulse signals, where M is an integer equal to or greater than 1, wherein said sync detection means comprising: reset means for generating a reset pulse in response to every M pulses of said PLL input pulse signal; counter means arranged to be incremented in response to each of said VFO output pulses for producing a count value and resetting the count value to zero in response to said reset pulse; and comparator means for detecting a coincidence between said count value and a reference value, and in response thereto, generating said phase-alignment indicating signal.

Claim 6

A phase-locked loop comprising: phase detector means for receiving a PLL input pulse signal at frequency f 0 and for receiving a PLL output pulse signal of said phase-locked loop, said PLL input and output pulse signals being applied to said phase detector means for producing a control signal representative of a phase difference between said PLL input and output pulse signals; variable-frequency oscillator means responsive to said control signal for generating VFO output pulses having a frequency which is variable in accordance with said phase difference; frequency divider means for dividing the frequency of said VFO output pulses by N for generating said PLL output pulse signal, where N is an integer equal to or greater than 2; sync detection means for receiving said PLL input pulse signal and said VFO output pulses and detecting when M×N pulses are generated by said oscillator means during an interval in which M input pulses are received as said PLL input pulse signal, and in response thereto, generating an output signal indicating that a phase alignment is established between said PLL input and output pulse signals, where M is an integer equal to or greater than 1, wherein said sync detection means comprising: reset means for generating a reset pulse in response to every M pulses of said PLL input pulse signal; counter means arranged to be incremented in response to each of said VFO output pulses for producing a count value and resetting the count value to zero in response to said reset pulse; and comparator means for detecting a coincidence between said count value and a reference value, and in response thereto, generating said phase-alignment indicating signal.