Patent US5476807A successfully refreshed from Google Patents.
US5476807A
Expired / Lapsed
US
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Method for forming fine patterns in a semiconductor device
Assignee: Samsung Electronics Co Ltd
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Filing: 1994-04-14
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Granted: 1995-12-19
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Expires: 2014-04-14
Abstract
Abstract A method for forming a fine pattern, e.g., for forming the storage electrodes of the capacitors of the memory cells of semiconductor memory devices, which includes the steps of depositing a mask layer on the layer to be patterned, depositing a photoresist layer on the mask layer, patterning the photoresist layer, to thereby form a photoresist pattern, anisotropically etching the mask layer, using the photoresist pattern as an etching mask, to thereby form a mask layer pattern, wherein etch by-products are formed on sidewalls of a composite layer comprised of the photoresist pattern and the mask layer pattern, and, etching the layer to be patterned using the composite layer and the etch by-products as an etching mask, to thereby form a fine pattern. The mask layer is made of a material, e.g., a high-temperature oxide, having different physical properties than that of the photoresist. Further, the anisotropic etching process is preferably carried out by means of a plasma etching process using a mixture of CF 4 , CHF 4 , and Ar gases, with the amount of the etch by-products being controllably adjusted by the ratio of these gases, and/or by controllably adjusting the time, temperature, and/or pressure parameters of this anisotropic etching process.
Inventors
- 👤 Kang-hyun Lee
- 👤 Jong-Seo Hong
- 👤 Hyoung-sub Kim
- 👤 Jae-ho Kim
- 👤 Min-seog Han
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:39
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10D; H10D1/00; H10D1/01; H10D1/041; H10D1/043; H10D1/60; H10D1/68; H10D1/692; H10D1/711; H10D1/714; H10P; H10P76/00; H10P76/40; H10P76/408; H10P76/4085
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
209 words
A method for manufacturing a semiconductor memory device, comprising the steps of: providing a semiconductor substrate in which a transistor having a gate and source/drain regions is formed; forming a first insulating layer on said semiconductor substrate; forming an interlayer insulating layer on said first insulating layer; forming an etch-blocking layer on said interlayer insulating layer; forming a second insulating layer on said etch-blocking layer; selectively etching said first insulating layer, said interlayer insulating layer, said etch-blocking layer, and said second insulating layer, to thereby form contact holes to expose said source/drain regions; forming a conductive layer on the surface of the resultant structure, including surface portions defining said contact holes; depositing a mask layer on said conductive layer; depositing a photoresist layer on said mask layer; patterning said photoresist layer in accordance with a capacitor storage electrode pattern, to thereby form a photoresist pattern; anisotropically etching said mask layer, using said photoresist pattern as an etching mask, to thereby form a mask layer pattern, wherein etch by-products are formed on sidewalls of a composite layer comprised of said photoresist pattern and said mask layer pattern; and, etching said conductive layer using said composite layer and said etch by-products as an etching mask, to thereby form a fine pattern.
Claim 2
Independent Claim
209 words
A method for manufacturing a semiconductor memory device, comprising the steps of: providing a semiconductor substrate in which a transistor having a gate and source/drain regions is formed; forming a first insulating layer on said semiconductor substrate; forming an interlayer insulating layer on said first insulating layer; forming an etch-blocking layer on said interlayer insulating layer; forming a second insulating layer on said etch-blocking layer; selectively etching said first insulating layer, said interlayer insulating layer, said etch-blocking layer, and said second insulating layer, to thereby form contact holes to expose said source/drain regions; forming a conductive layer on the surface of the resultant structure, including surface portions defining said contact holes; depositing a mask layer on said conductive layer; depositing a photoresist layer on said mask layer; patterning said photoresist layer in accordance with a capacitor storage electrode pattern, to thereby form a photoresist pattern; anisotropically etching said mask layer, using said photoresist pattern as an etching mask, to thereby form a mask layer pattern, wherein etch by-products are formed on sidewalls of a composite layer comprised of said photoresist pattern and said mask layer pattern; and, etching said conductive layer using said composite layer and said etch by-products as an etching mask, to thereby form a fine pattern.
Claim 3
Dependent Claim
21 words
The method as set forth in claim 1, further comprising the step of removing said composite layer and said etch by-products.
Claim 4
Dependent Claim
18 words
The method as set forth in claim 2, wherein said etch by-products together comprise a residual polymer layer.
Claim 5
Independent Claim
105 words
A method for forming a fine pattern, comprising the steps of: depositing a mask layer on said layer to be patterned; depositing a photoresist layer on said mask layer; patterning said photoresist layer, to thereby form a photoresist pattern; anisotropically etching said mask layer, using said photoresist pattern as an etching mask, to thereby form a mask layer pattern, wherein etch by-products are formed on sidewalls of a composite layer comprised of said photoresist pattern and said mask layer pattern; and, etching said layer to be patterned using said composite layer and said etch by-products as an etching mask, to thereby form a fine pattern.
Claim 6
Independent Claim
105 words
A method for forming a fine pattern, comprising the steps of: depositing a mask layer on said layer to be patterned; depositing a photoresist layer on said mask layer; patterning said photoresist layer, to thereby form a photoresist pattern; anisotropically etching said mask layer, using said photoresist pattern as an etching mask, to thereby form a mask layer pattern, wherein etch by-products are formed on sidewalls of a composite layer comprised of said photoresist pattern and said mask layer pattern; and, etching said layer to be patterned using said composite layer and said etch by-products as an etching mask, to thereby form a fine pattern.
Claim 7
Dependent Claim
27 words
The method as set forth in claim 4, wherein said mask layer is made of a material having different physical properties than that of said photoresist layer.
Claim 8
Dependent Claim
19 words
The method as set forth in claim 5, wherein said mask layer is made of a high-temperature oxide material.
Claim 9
Dependent Claim
31 words
The method as set forth in claim 6, wherein the amount of said etch by-products is controllably adjusted by means of varying one or more parameters of said anisotropically etching process.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-12-18 | 1999-06-19 | 1999-12-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-12-18 | 2003-06-19 | 2003-12-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-12-18 | 2007-06-19 | 2007-12-19 | $7700.00 | Window Closed / Lapsed |