US5475273A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Smart power integrated circuit with dynamic isolation
Assignee: CONSORZIO PER LA RICERCA
•
Filing: 1992-12-07
•
Granted: 1995-12-12
•
Expires: 2012-12-07
Abstract
Abstract A smart power integrated circuit with dynamic isolation. A P-type isolation region surrounds the small signal devices (npn bipolar transistors and possibly other devices). This isolation region is held at ground in normal operation; but one or more pilot circuits continually monitor the collector voltages of the small-signal and power npn transistors, and instantly reconnect this isolation region, in real time, to the lowest collector voltage, whenever any of the collector voltages go below ground. Preferably a large capacitor provides a dedicated supply to the pilot circuit, so that the reconnection operation can proceed even when a power supply glitch occurs.
Inventors
- 👤 Mario Paparo
- 👤 Raffaele Zambrano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:38
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60
Claims Analysis
Total Claims: 36
Claim 1
Independent Claim
170 words
An integrated circuit, comprising: at least one power transistor integrated in a monolithic body of semiconductor material with one or more small-signal transistors; at least one p-type isolation region interposed between said power transistor and at least one of said small-signal transistors; a first switch operable to connect said p-type isolation region to ground; a second switch operable to connect said p-type isolation region to an n-type region of said power transistor; a third switch operable to connect said p-type isolation region to an n-type region of said small-signal transistor; a pilot circuit operatively connected to said n-type region of said small-signal transistor, to said n-type region of said power transistor, to ground, and to said first, second, and third switches; wherein said pilot circuit monitors the voltage of said n-type regions of said power and small-signal transistors, and accordingly operates said switches to connect said p-type isolation region to the lowest voltage of: ground; said n-type region of said power transistor; and said n-type region of said small-signal transistor.
Claim 2
Dependent Claim
170 words
An integrated circuit, comprising: at least one power transistor integrated in a monolithic body of semiconductor material with one or more small-signal transistors; at least one p-type isolation region interposed between said power transistor and at least one of said small-signal transistors; a first switch operable to connect said p-type isolation region to ground; a second switch operable to connect said p-type isolation region to an n-type region of said power transistor; a third switch operable to connect said p-type isolation region to an n-type region of said small-signal transistor; a pilot circuit operatively connected to said n-type region of said small-signal transistor, to said n-type region of said power transistor, to ground, and to said first, second, and third switches; wherein said pilot circuit monitors the voltage of said n-type regions of said power and small-signal transistors, and accordingly operates said switches to connect said p-type isolation region to the lowest voltage of: ground; said n-type region of said power transistor; and said n-type region of said small-signal transistor.
Claim 3
Dependent Claim
16 words
The integrated circuit of claim 1, wherein said first switch comprises a metal gate NMOS transistor.
Claim 4
Dependent Claim
16 words
The integrated circuit of claim 1, wherein said first switch comprises a double diffused NMOS transistor.
Claim 5
Dependent Claim
17 words
The integrated circuit of claim 1, wherein said second switch comprises a double-diffused thin-gate-oxide metal-gate NMOS transistor.
Claim 6
Dependent Claim
23 words
The integrated circuit of claim 1, wherein said first switch comprises a metal gate NMOS transistor having a laterally uniform channel dopant concentration.
Claim 7
Dependent Claim
31 words
The integrated circuit of claim 1, wherein said first switch comprises a metal gate NMOS transistor having a laterally uniform channel dopant concentration, and said second switch comprises a bipolar transistor.
Claim 8
Dependent Claim
22 words
The integrated circuit of claim 1, further comprising a capacitor connected to store charge and to provide power to said pilot circuit.
Claim 9
Dependent Claim
180 words
An integrated circuit, comprising: at least one power transistor integrated in a monolithic body of semiconductor material with one or more small-signal transistors; at least one p-type isolation region interposed between said power transistor and at least one of said small-signal transistors; a first switch operable to connect said p-type isolation region to ground; a second switch operable to connect said p-type isolation region to an n-type region of said power transistor; a third switch operable to connect said p-type isolation region to an n-type region of said small-signal transistor; a pilot circuit operatively connected to said n-type region of said small-signal transistor, to said n-type region of said power transistor, to ground, to said p-type isolation region, and to said first, second, and third switches; wherein said pilot circuit monitors the voltage of said p-type isolation region and said n-type regions of said power and small-signal transistors, and accordingly operates said switches to connect said p-type isolation region to the lowest voltage of: ground; said n-type region of said power transistor; and said n-type region of said power transistor.
Claim 10
Dependent Claim
180 words
An integrated circuit, comprising: at least one power transistor integrated in a monolithic body of semiconductor material with one or more small-signal transistors; at least one p-type isolation region interposed between said power transistor and at least one of said small-signal transistors; a first switch operable to connect said p-type isolation region to ground; a second switch operable to connect said p-type isolation region to an n-type region of said power transistor; a third switch operable to connect said p-type isolation region to an n-type region of said small-signal transistor; a pilot circuit operatively connected to said n-type region of said small-signal transistor, to said n-type region of said power transistor, to ground, to said p-type isolation region, and to said first, second, and third switches; wherein said pilot circuit monitors the voltage of said p-type isolation region and said n-type regions of said power and small-signal transistors, and accordingly operates said switches to connect said p-type isolation region to the lowest voltage of: ground; said n-type region of said power transistor; and said n-type region of said power transistor.
Claim 11
Dependent Claim
16 words
The integrated circuit of claim 8, wherein said first switch comprises a metal gate NMOS transistor.
Claim 12
Dependent Claim
22 words
The integrated circuit of claim 8, further comprising a capacitor connected to store charge and to provide power to said pilot circuit.
Claim 13
Dependent Claim
16 words
The integrated circuit of claim 8, wherein said first switch comprises a double diffused NMOS transistor.
Claim 14
Dependent Claim
17 words
The integrated circuit of claim 8, wherein said second switch comprises a double-diffused thin-gate-oxide metal-gate NMOS transistor.
Claim 15
Dependent Claim
31 words
The integrated circuit of claim 8, wherein said first switch comprises a metal gate NMOS transistor having a laterally uniform channel dopant concentration, and said second switch comprises a bipolar transistor.
Claim 16
Dependent Claim
22 words
The integrated circuit of claim 8, further comprising a capacitor connected to store charge and to provide power to said pilot circuit.
Claim 17
Dependent Claim
205 words
An integrated circuit including a solid state two-way switch, comprising: first and second power transistors, each operable to connect a common substrate region, of a first conductivity type, to a respective other region of said first conductivity type; a first control circuit operatively connected to control said first power transistor, and a second control circuit operatively connected to control said second power transistor; said power transistors and control circuits all being integrated in a common body of monocrystalline semiconductor material, and said first power transistor being isolated from said first control circuit by a first isolation region, and said second power transistor being isolated from said second control circuit by a second isolation region; said isolation regions both having a second conductivity type; said first and second control circuits comprising first and second pilot circuits respectively, each connected to first and second supply voltages, and to a respective one of said isolation regions, and to said power transistor and control circuit, and to three respective switches; wherein each said pilot circuit operates said three respective switches to connect said respective isolation region to the most extreme voltage of: said first supply voltage; said respective other region of said power transistor; and said respective control circuit.
Claim 18
Dependent Claim
205 words
An integrated circuit including a solid state two-way switch, comprising: first and second power transistors, each operable to connect a common substrate region, of a first conductivity type, to a respective other region of said first conductivity type; a first control circuit operatively connected to control said first power transistor, and a second control circuit operatively connected to control said second power transistor; said power transistors and control circuits all being integrated in a common body of monocrystalline semiconductor material, and said first power transistor being isolated from said first control circuit by a first isolation region, and said second power transistor being isolated from said second control circuit by a second isolation region; said isolation regions both having a second conductivity type; said first and second control circuits comprising first and second pilot circuits respectively, each connected to first and second supply voltages, and to a respective one of said isolation regions, and to said power transistor and control circuit, and to three respective switches; wherein each said pilot circuit operates said three respective switches to connect said respective isolation region to the most extreme voltage of: said first supply voltage; said respective other region of said power transistor; and said respective control circuit.
Claim 19
Dependent Claim
19 words
The integrated circuit of claim 15, wherein a first one of said switches comprises a metal gate NMOS transistor.
Claim 20
Dependent Claim
19 words
The integrated circuit of claim 15, wherein a first one of said switches comprises a double diffused NMOS transistor.
Claim 21
Dependent Claim
20 words
The integrated circuit of claim 15, wherein a second one of said switches comprises a double-diffused thin-gate-oxide metal-gate NMOS transistor.
Claim 22
Dependent Claim
26 words
The integrated circuit of claim 15, wherein a first one of said switches comprises a metal gate NMOS transistor having a laterally uniform channel dopant concentration.
Claim 23
Dependent Claim
37 words
The integrated circuit of claim 15, wherein a first one of said switches comprises a metal gate NMOS transistor having a laterally uniform channel dopant concentration, and a second one of said switches comprises a bipolar transistor.
Claim 24
Dependent Claim
84 words
The integrated circuit of claim 15, wherein each pilot circuit comprises a NOR logic circuit whose output pilots a first switch of said switches, and a first and a second voltage comparator, whose "-" inputs are connected with said other region of said power transistor respectively, and whose "+" inputs are connected with said isolation region, and whose outputs pilot a third switch and a first input of said NOR circuit and a second switch and a second input of said NOR circuit respectively.
Claim 25
Dependent Claim
22 words
The integrated circuit of claim 15, further comprising a capacitor connected to store charge and to provide power to said pilot circuit.
Claim 26
Dependent Claim
156 words
An integrated circuit, powered by negative supply voltages and a positive ground connection, comprising: at least one power transistor integrated in a monolithic body of semiconductor material with one or more small-signal transistors; at least one n-type isolation region interposed between said power transistor and at least one of said small-signal transistors; a first switch operable to connect said n-type isolation region to ground; a second switch operable to connect said n-type isolation region to a p-type region of said power transistor; a third switch operable to connect said n-type isolation region to a p-type region of said small-signal transistor; a pilot circuit connected to said p-type region of said power transistor, to ground, and to said first, second, and third switches; wherein said pilot circuit operates said switches to connect said n-type isolation region to the highest voltage of: ground; said p-type region of said power transistor; and said p-type region of said small-signal transistor.
Claim 27
Dependent Claim
156 words
An integrated circuit, powered by negative supply voltages and a positive ground connection, comprising: at least one power transistor integrated in a monolithic body of semiconductor material with one or more small-signal transistors; at least one n-type isolation region interposed between said power transistor and at least one of said small-signal transistors; a first switch operable to connect said n-type isolation region to ground; a second switch operable to connect said n-type isolation region to a p-type region of said power transistor; a third switch operable to connect said n-type isolation region to a p-type region of said small-signal transistor; a pilot circuit connected to said p-type region of said power transistor, to ground, and to said first, second, and third switches; wherein said pilot circuit operates said switches to connect said n-type isolation region to the highest voltage of: ground; said p-type region of said power transistor; and said p-type region of said small-signal transistor.
Claim 28
Dependent Claim
29 words
The integrated circuit of claim 23, wherein said first switch comprises a PMOS transistor having a laterally uniform channel dopant concentration, and said second switch comprises a bipolar transistor.
Claim 29
Independent Claim
223 words
A method for operating an integrated circuit which includes at least one power transistor integrated in a monolithic body of semiconductor material with one or more small-signal transistors, and at least one p-type isolation region interposed between said power transistor and at least one of said small-signal transistors, comprising the steps of, in on-chip circuitry: (a.) monitoring, substantially continually in a pilot circuit on the integrated circuit, the voltage of an N-type portion of the power transistor; (b.) monitoring, substantially continually in a pilot circuit on the integrated circuit, the voltage of an N-type region of at least one of said small-signal transistors of the integrated circuit; (c.) operating a first N-channel switching transistor, under control of said pilot circuit, to operatively connect said p-type isolation region to said N-type portion of the power transistor, at each instant, if and only if the voltage of said N-type portion of the power transistor is below ground; and (d.) operating a second N-channel switching transistor, under control of said pilot circuit, to operatively connect the p-type isolation region to said N-type portion of at least one of said small-signal transistors, at each instant, if and only if the voltage of said N-type portion of said small-signal transistor is below ground; and (e.) operatively connecting said p-type isolation region to ground at substantially all other times.
Claim 30
Independent Claim
223 words
A method for operating an integrated circuit which includes at least one power transistor integrated in a monolithic body of semiconductor material with one or more small-signal transistors, and at least one p-type isolation region interposed between said power transistor and at least one of said small-signal transistors, comprising the steps of, in on-chip circuitry: (a.) monitoring, substantially continually in a pilot circuit on the integrated circuit, the voltage of an N-type portion of the power transistor; (b.) monitoring, substantially continually in a pilot circuit on the integrated circuit, the voltage of an N-type region of at least one of said small-signal transistors of the integrated circuit; (c.) operating a first N-channel switching transistor, under control of said pilot circuit, to operatively connect said p-type isolation region to said N-type portion of the power transistor, at each instant, if and only if the voltage of said N-type portion of the power transistor is below ground; and (d.) operating a second N-channel switching transistor, under control of said pilot circuit, to operatively connect the p-type isolation region to said N-type portion of at least one of said small-signal transistors, at each instant, if and only if the voltage of said N-type portion of said small-signal transistor is below ground; and (e.) operatively connecting said p-type isolation region to ground at substantially all other times.
Claim 31
Dependent Claim
17 words
The method of claim 25, wherein said first N-channel switching transistor comprises a metal gate NMOS transistor.
Claim 32
Dependent Claim
17 words
The method of claim 25, wherein said first N-channel switching transistor comprises a double diffused NMOS transistor.
Claim 33
Dependent Claim
18 words
The method of claim 25, wherein said second N-channel switching transistor comprises a double-diffused thin-gate-oxide metal-gate NMOS transistor.
Claim 34
Dependent Claim
24 words
The method of claim 25, wherein said first N-channel switching transistor comprises a metal gate NMOS transistor having a laterally uniform channel dopant concentration.
Claim 35
Independent Claim
233 words
A method for operating an integrated circuit, powered by negative supply voltages and a positive ground connection, which includes at least one power transistor integrated in a monolithic body of semiconductor material with one or more small-signal transistors, and at least one N-type isolation region interposed between said power transistor and at least one of said small-signal transistors, comprising the steps of, in on-chip circuitry: (a.) monitoring, substantially continually in a pilot circuit on the integrated circuit, the voltage of a P-type portion of the power transistor; (b.) monitoring, substantially continually in a pilot circuit on the integrated circuit, the voltage of a P-type region of at least one of said small-signal transistors of the integrated circuit; (c.) operating a first P-channel switching transistor, under control of said pilot circuit, to operatively connect the N-type isolation region to said P-type portion of the power transistor, at each instant, if and only if the voltage of said P-type portion of the power transistor is above ground; and (d.) operating a second N-channel switching transistor, under control of said pilot circuit, to operatively connect the N-type isolation region to said N-type portion of at least one of said small-signal transistors, at each instant, if and only if the voltage of said N-type portion of the small-signal transistor is below ground; and (e.) operatively connecting the N-type isolation region to ground at substantially all other times.
Claim 36
Independent Claim
233 words
A method for operating an integrated circuit, powered by negative supply voltages and a positive ground connection, which includes at least one power transistor integrated in a monolithic body of semiconductor material with one or more small-signal transistors, and at least one N-type isolation region interposed between said power transistor and at least one of said small-signal transistors, comprising the steps of, in on-chip circuitry: (a.) monitoring, substantially continually in a pilot circuit on the integrated circuit, the voltage of a P-type portion of the power transistor; (b.) monitoring, substantially continually in a pilot circuit on the integrated circuit, the voltage of a P-type region of at least one of said small-signal transistors of the integrated circuit; (c.) operating a first P-channel switching transistor, under control of said pilot circuit, to operatively connect the N-type isolation region to said P-type portion of the power transistor, at each instant, if and only if the voltage of said P-type portion of the power transistor is above ground; and (d.) operating a second N-channel switching transistor, under control of said pilot circuit, to operatively connect the N-type isolation region to said N-type portion of at least one of said small-signal transistors, at each instant, if and only if the voltage of said N-type portion of the small-signal transistor is below ground; and (e.) operatively connecting the N-type isolation region to ground at substantially all other times.
References Cited (Backward Citations)
US3931634A
Cited
US4336466A
Cited
US4426658A
Cited
US4496849A
Cited
US4800418A
Cited
JPS61101068A
Cited
US4941030A
Cited
US4972247A
Cited
US4675561A
Cited
US4890149A
Cited
JPS63155757A
Cited
US4789917A
Cited
JPS6477155A
Cited
US5124761A
Cited
US4992836A
Cited
US5051612A
Cited
US5132866A
Cited
EP0432058A1
Cited
US5159207A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-12-11 | 1999-06-12 | 1999-12-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-12-11 | 2003-06-12 | 2003-12-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-12-11 | 2007-06-12 | 2007-12-12 | $7700.00 | Window Closed / Lapsed |