Contact structure of an interconnection layer for a semiconductor device and a multilayer interconnection SRAM

Claim 1

An SRAM comprising memory cells, each including a pair of first and second CMOS inverters connected so as to constitute a flip-flop circuit, and first and second MOS transfer transistors connected to node points of the flip-flop circuit, respectively, said first CMOS inverter comprising a first MOS drive transistor of a first conductivity type formed on a main surface of a silicon substrate, and a first thin film transistor of a second conductivity type formed on a surface of an interlevel insulating layer formed on said main surface of the silicon substrate, said second CMOS inverter comprising a second MOS drive transistor of the first conductivity type formed on the main surface of the silicon substrate, and a second thin film transistor of the second conductivity type formed on said surface of the interlevel insulating layer, and said first MOS transfer transistor and said second MOS transfer transistor being formed on the main surface of the silicon substrate, said SRAM comprising: first interconnection means for connecting a gate electrode of said first MOS drive transistor, a source/drain region of said second MOS transfer transistor, and a source/drain region of said second thin film transistor; and second interconnection means for connecting a gate electrode of said second MOS drive transistor, a source/drain region of said first MOS transfer transistor, and a source/drain region of said first thin film transistor; said first interconnection means being embedded in an opening formed in said interlevel insulating layer and comprising a silicon plug connected to a gate electrode of said first MOS drive transistor and to a source/drain region of said second MOS transfer transistor, an intermediate conductive layer of either refractory metal or refractory metal silicide formed on a surface of said silicon plug, and an interconnection layer of polycrystalline silicon extending on a surface of said interlevel insulating layer and electrically connecting said intermediate conductive layer and a source/drain region of said second thin film transistor, and said second interconnection means being embedded in a second opening formed in said interlevel insulating layer and comprising a second silicon plug connected to a gate electrode of said second MOS drive transistor and to a source/drain region of said first MOS transfer transistor, a second intermediate conductive layer of either refractory metal or refractory metal silicide formed on the surface of said second silicon plug, and a second interconnection layer of polycrystalline silicon extending on a surface of said interlevel insulating layer and electrically connecting said second intermediate conductive layer and a source/drain region of said first thin film transistor.