US5473564A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory card having an integrated circuit for the secure counting down of units
Assignee: Gemplus SA
•
Filing: 1994-03-31
•
Granted: 1995-12-05
•
Expires: 2014-03-31
Abstract
Abstract In a memory card designed to count down a number of units by successive programming of non-volatile, electrically erasable and electrically programmable memory cells, the memory is organized into N rows of P cells, the weight of the cells of one row in the account being P times the weight of the next-ranking row. The countdown procedure is recurrent and consists in making a search, in scanning the memory according to the rising order of weights, of an erased cell, programming this cell and an erased cell and then erasing the entire row having an immediately lower rank unless the erased cell is located in the first row, and in recommencing this recurrent procedure until an erased cell is found in the first line. The auxiliary cell enables the detection of an abnormal interruption of the recurrent procedure and the restoring of the exact account of the memory which could have been distorted by this abnormal interruption.
Inventors
- 👤 Jacek A. Kowalski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 09:41
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/102; G11C16/105; G11C16/12; G11C16/14; G11C16/16
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
114 words
A integrated circuit for a memory card comprising a non-volatile memory organized into a network of N zones of P cells with means for the selective programming of an i, j ranking cell of the memory, i designating the rank of the zone and j the rank of the cell in the zone, and means for the selective erasure of all the cells of a selected zone wherein said circuit comprises, associated with each i ranking zone, only one non-volatile auxiliary memory cell which is programmed at the same time as any other cell of the i ranking zone and is erased at the same time as the cells of the i-1 ranking zone.
Claim 2
Dependent Claim
114 words
A integrated circuit for a memory card comprising a non-volatile memory organized into a network of N zones of P cells with means for the selective programming of an i, j ranking cell of the memory, i designating the rank of the zone and j the rank of the cell in the zone, and means for the selective erasure of all the cells of a selected zone wherein said circuit comprises, associated with each i ranking zone, only one non-volatile auxiliary memory cell which is programmed at the same time as any other cell of the i ranking zone and is erased at the same time as the cells of the i-1 ranking zone.
Claim 3
Dependent Claim
125 words
An integrated circuit according to claim 1, further including a cell address decoder whose heavyweight values are used to select an i ranking zone and whose lightweight values are used to select a j ranking cell in the selected zone, wherein it includes circuits controlled by the heavyweight outputs of the decoder so that, when the i ranking zone is selected, potentials for the programming potentials of a cell of the i ranking zone and of the auxiliary i ranking cell can be applied to these cells and so that, again when the row i is selected, it is possible to apply potentials for the erasing of the row having the rank i-1 (i>1) and potentials for the erasing of the auxiliary i ranking cell.
Claim 4
Dependent Claim
101 words
An integrated circuit according to claim 1, wherein the non-volatile memory cells of the network and the auxiliary cells each comprise a selection transistor and a floating-gate transistor, the floating-gate transistors of the cells of an i-1 ranking zone of the network having a control gate connected to the control gate of the floating-gate transistor of the auxiliary cell of the zone i, the sources of the floating-gate transistors of the network being connected to a first common conductor and the sources of the auxiliary floating-gate transistors being connected to a second common conductor that is independent of the first one.
Claim 5
Dependent Claim
90 words
An integrated circuit according to claim 3, wherein the control gates of the floating-gate transistors of the i ranking zone are connected by an i ranking control transistor to a third common conductor enabling the application of a reading, erasing or programming potential to the i ranking cells, and wherein the control gate of the i ranking auxiliary floating-gate transistor is connected by an auxiliary i ranking control transistor to a fourth common conductor enabling the application of a reading, programming or erasure potential to the i ranking auxiliary cell.
Claim 6
Dependent Claim
28 words
An integrated circuit according to claim 4, wherein the i ranking control transistor and the i ranking auxiliary control transistor are controlled by an i ranking word line.
Claim 7
Dependent Claim
128 words
An integrated circuit according to claim 3, wherein the selection transistors corresponding to an i ranking zone of the network are controlled by an i ranking word line, and connect the drains of the floating-gate transistors having a same rank j to one and the same bit line having the rank j, wherein the selection transistor of the i ranking auxiliary cell is controlled by the i ranking word line and connects the floating-gate transistor of this auxiliary cell to an auxiliary bit line common to all the auxiliary cells and wherein, to this auxiliary bit line, there is applied the same potential, in programming or erasing mode, as the potential applied to a bit line corresponding to a cell to be programmed or erased in the network.
Claim 8
Dependent Claim
30 words
An integrated circuit according to claim 6, wherein the auxiliary bit line is connected to an output of the circuit in order to read the state of the auxiliary cells.
Claim 9
Dependent Claim
11 words
A memory card using an integrated circuit according to claim 1.
References Cited (Backward Citations)
FR321727A
Cited
FR519847A
Cited
US4881199A
Cited
US4896298A
Cited
US5097146A
Cited
US4868489A
Cited
US4916333A
Cited
US4827450A
Cited
US5022001A
Cited
US5060198A
Cited
US4890187A
Cited
US5003371A
Cited
US5191498A
Cited
US5060261A
Cited
EP0447856A1
Cited
WO1992006451A1
Cited
WO1992015074A1
Cited
WO1992015096A1
Cited
WO1993005513A1
Cited
WO1993015477A1
Cited
US5414664A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-12-04 | 1999-06-05 | 1999-12-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-12-04 | 2003-06-05 | 2003-12-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-12-04 | 2007-06-05 | 2007-12-05 | $7700.00 | Window Closed / Lapsed |