Nonvolatile semiconducteur memory

Claim 2

A memory according to claim 1, wherein said memory cells (30) within each of said blocks are disposed in a matrix.

Claim 3

A memory according to claim 2, wherein the drains (16) of said memory cells (30) disposed in a column direction within each of said blocks are commonly connected to constitute a common drain (43).

Claim 4

A memory according to claim 3, wherein said common drains within each of said blocks are connected, via a corresponding one of first switching elements (42-1 to 42-n), to a corresponding one of data lines (DL1 to DLn) for transfer of said write signal and read out data.

Claim 5

A memory according to claim 4, wherein each of said data lines is connected to a data input circuit (36) via a corresponding one of second switching elements (34-1 to 34-n).

Claim 6

A memory according to claim 4, wherein said first switching elements (42-1 to 42-n) within each of said blocks are connected to a corresponding one of block select decoders (45-1 to 45-k) to be commonly turned on and off by an output from said block select decoder.

Claim 7

A memory according to claim 5, wherein said second switching elements (34-1 to 34-n) are connected to a column decoder (33) so that at least one of said second switching elements is turned on by an output of said column decoder.

Claim 8

A memory according to claim 4, wherein said data line corresponding to said memory cells (30) disposed in one column within one of said blocks and said data line corresponding to said memory cells disposed in said one column within another of said blocks are connected to said data input circuit 36 via a corresponding one of said second switching elements (34-1 to 34-n).

Claim 9

A memory according to claim 8, wherein said second switching elements (34-1 to 34-n) are connected to a column decoder (33) so that at least one of said second switching elements is turned on by an output of said column decoder.

Claim 10

A memory according to claim 8, wherein said first switching elements (42-1 to 42-n) within each of said blocks are connected to a corresponding one of block select decoders (45-1 to 45-k) to be commonly turned on and off by an output from said block select decoder.

Claim 11

A memory according to claim 9, wherein said first switching elements (42-1 to 42-n) within each of said blocks are connected to a corresponding one of block select decoders (45-1 to 45-k) to be commonly turned on and off by an output from said block select decoder.

Claim 12

A memory according to claim 11, wherein said floating gate transistor (30) includes an erase gate (12) to which said erase signal of a positive voltage is applied from a corresponding one of said erase signal applying means (44-1 to 44-k) when data is erased, to thereby pull out electrons from said floating gate (11).

Claim 13

A memory according to claim 11, wherein said floating gate transistor (30) has no erase gate for pulling out electrons from said floating gate (11), but said floating gate transistor pulls said electrons into said source (15), and said erase signal applying means (44-2, 44-3) applies said erase signal of a positive voltage to the source (16) of each of said floating gate transistors.

Claim 14

A memory according to claim 12, wherein the sources (15) of said floating gate transistors (30) in the same column within one of said blocks are commonly connected.

Claim 15

A memory according to claim 13, wherein the sources (15) of said floating gate transistors (30) in the same column within one of said blocks are commonly connected.

Claim 16

A memory according to claim 14, wherein the sources (15) of the memory cells (30) in the corresponding columns of adjacent ones of said blocks are connected in common.

Claim 17

A memory according to claim 15, wherein the sources (16) of the memory cells (30) in the corresponding columns of adjacent ones of said blocks are connected to a corresponding one of common source lines (V SS* ) via a corresponding one of third switching elements (47).

Claim 18

A memory according to claim 15, wherein the sources within each of said blocks are connected to a corresponding one of common source lines (V SS*2 , V SS*3 ).

Claim 19

The memory according to claim 4, wherein: said data line (DL1, DL2, ...) is provided to each memory cell array in the column direction.

Claim 20

The memory according to claim 4, wherein: of said data line (DL23, DL45, ...) is provided with respect to two memory cell arrays in the column direction.

Claim 21

The memory cell according to claim 20, wherein: applying a signal to said source is performed by a source decoder (SD).

Claim 22

A non-volatile semiconductor memory comprising: a plurality of blocks (31-1 to 31-b; B1, B2, ...) each having a memory cell array including non-volatile semiconductor memory cells (30) each having a gate insulation film (19), said memory cells (30) each storing data therein by injecting charges through said insulating film, said memory cells being arranged in a matrix fashion with a plurality of row lines and a plurality of a common drain lines (43), said blocks (31-1 to 31-k) each having first switching elements (42-1 to 42-n) each connecting said plurality of common drain lines (43) to a plurality of common bit lines (DL1 to DLn), row decoders (32-1 to 32-k) for selecting said row lines, column decoder (33) for selecting said common bit lines (DL1 to DLn), first block select decoders (45-1, 45-2) for selecting said first switching elements (42-1, 42-2, ...), second block select decoder (44-2, 44-3) for selecting common source (V SS* ) of said memory cells (30) within each of said blocks, thereby writing data are only applied to said cells (30) in said selected blocks and not applied to said cells (30) in said non-selected blocks.

Claim 23

A non-volatile semiconductor memory comprising: a plurality of blocks (B1, B2) each having a memory cell array including non-volatile memory cells (30) being arranged in a matrix fashion with a plurality of row lines (WL5, WL6, ...), a plurality of drain lines (43) and a plurality of source liens (46), said each two adjacent memory cells being connected by connecting one drain to other drain and one source to other source each other along a direction of row lines, said blocks each having first switching element (42-1 - 42-n) each connecting said plurality of drain lines (43) to a plurality of common bit lines (DL23, DL45, ...), a second switching elements (47) each connecting said plurality of souce lines to said plurality of common souce lines (V SS* 1, ...), a row decoders (32-2) for selecting said row lines (WL5, WL6, ...), a column decoder (33) for selecting said common bit lines (DL23, DL45...), a source decoder (SD) for selecting said common source lines (V SS* 1, V SS* 2), first block select deocder (45-1, 45-2...) for selecting said first switching elements, second block select decoders (44-2, 44-3, ...) for selecting said common source lines V SS* 1, V SS* 2), thereby writing data are only applied to said cells (30) in said selected blocks and not applied to said cells (30) in said non-selected blocks.