Method of manufacturing a floating gate memory device

Claim 1

A method of manufacturing a semiconductor memory device, comprising: a first step of forming a first insulating film at a position corresponding to a tunnel region on a surface of a semiconductor substrate, and forming a second insulating film having a thickness larger than that of said first insulating film on portions other than said tunnel region so as to be in contact with said first insulating film, said first and second insulating films constituting a gate insulating film; a second step of forming a floating gate on said gate insulating film including a portion on said tunnel region, said floating gate being comprised of a first conductive layer in contact with said gate insulating film and a second conductive layer formed on said first conductive layer, an impurity concentration of said first conductive layer being set to be lower than that of said second conductive layer; and a third step of forming a third insulating film between said first and second conductive layers constituting said floating gate, said third insulating film being formed to prevent diffusion of impurity from said second conductive layer to said first insulating layer and having a thickness which enable movement of carriers between the first and second conductive layers.

Claim 2

A method of manufacturing a semiconductor memory device, comprising: a first step of forming a first insulating film at a position corresponding to a tunnel region on a surface of a semiconductor substrate, and forming a second insulating film having a thickness larger than that of said first insulating film on portions other than said tunnel region so as to be in contact with said first insulating film, said first and second insulating films constituting a gate insulating film; a second step of forming a floating gate on said gate insulating film including a portion on said tunnel region, said floating gate being comprised of a first conductive layer in contact with said gate insulating film and a second conductive layer formed on said first conductive layer, an impurity concentration of said first conductive layer being set to be lower than that of said second conductive layer; and a third step of forming a third insulating film between said first and second conductive layers constituting said floating gate, said third insulating film being formed to prevent diffusion of impurity from said second conductive layer to said first insulating layer and having a thickness which enable movement of carriers between the first and second conductive layers.

Claim 3

A method of manufacturing a semiconductor memory device, comprising: a first step of forming a first insulating film at a position corresponding to a tunnel region i on a surface of a semiconductor substrate, and forming a second insulating film having a thickness larger than that of said first insulating film on portions other than said tunnel region so as to be in contact with said first insulating film, said first and second insulating films constituting a gate insulating film; a second step of forming a first conductive film having a low impurity concentration on said gate insulating film, said first conductive film constituting a floating gate; a third step of forming a barrier layer on said first conductive film at least in a region broader than that of said first insulating film forming said gate insulating film; and a fourth step of diffusing an impurity from a surface of said first conductive film so as to set an impurity concentration of an outer portion of a region corresponding to said barrier layer to be higher than that of an inner portion of said region corresponding to said barrier layer.

Claim 4

A method of manufacturing a semiconductor memory device, comprising: a first step of forming a first insulating film at a position corresponding to a tunnel region i on a surface of a semiconductor substrate, and forming a second insulating film having a thickness larger than that of said first insulating film on portions other than said tunnel region so as to be in contact with said first insulating film, said first and second insulating films constituting a gate insulating film; a second step of forming a first conductive film having a low impurity concentration on said gate insulating film, said first conductive film constituting a floating gate; a third step of forming a barrier layer on said first conductive film at least in a region broader than that of said first insulating film forming said gate insulating film; and a fourth step of diffusing an impurity from a surface of said first conductive film so as to set an impurity concentration of an outer portion of a region corresponding to said barrier layer to be higher than that of an inner portion of said region corresponding to said barrier layer.

Claim 5

A method of manufacturing a semiconductor memory device, comprising: a first step of forming a first insulating film at a position corresponding to a tunnel region on a surface of a semiconductor substrate, and forming a second insulating film having a thickness larger than that of said first insulating film on portions other than said tunnel region so as to be in contact with said first insulating film, said first and second insulating films constituting a gate insulating film; a second step of forming a floating gate on said gate insulating film including a portion on said tunnel region, wherein the floating gate is formed on said first and second insulating films, then forming a barrier layer in said floating gate at a position corresponding to said tunnel region, and diffusing an impurity into said floating gate to set an impurity concentration of a portion of said floating gate corresponding to said tunnel region, between said first insulating film, and said barrier layer, to be lower than that of other portions; and a third step of forming a control gate on said floating gate through a third insulating film.

Claim 6

A method of manufacturing a semiconductor memory device, comprising: a first step of forming a first insulating film at a position corresponding to a tunnel region on a surface of a semiconductor substrate, and forming a second insulating film having a thickness larger than that of said first insulating film on portions other than said tunnel region so as to be in contact with said first insulating film, said first and second insulating films constituting a gate insulating film; a second step of forming a floating gate on said gate insulating film including a portion on said tunnel region, wherein the floating gate is formed on said first and second insulating films, then forming a barrier layer in said floating gate at a position corresponding to said tunnel region, and diffusing an impurity into said floating gate to set an impurity concentration of a portion of said floating gate corresponding to said tunnel region, between said first insulating film, and said barrier layer, to be lower than that of other portions; and a third step of forming a control gate on said floating gate through a third insulating film.