US5468987A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device and method for forming the same
Assignee: Semiconductor Energy Laboratory Co Ltd
•
Filing: 1993-03-25
•
Granted: 1995-11-21
•
Expires: 2013-03-25
Abstract
Abstract In a thin-film insulated gate type field effect transistor having a metal gate in which the surface of the gate electrode is subjected to anodic oxidation, a silicon nitride film is provided so as to be interposed between the gate eiectrode and the gate insulating film to prevent invasion of movable ions into a channel, and also to prevent the breakdown of the gate insulating film due to a potential difference between the gate electrode and the channel region. By coating a specific portion of the gate eiectrode with metal material such as chrome or the like for the anodic oxidation, and then removing only the metal material such as chrome or the like together with the anodic oxide of the metal material such as chrome or the like, an exposed portion of metal gate (e.g. aluminum) is formed, and an upper wiring is connected to the exposed portion. Further, an aluminum oxide or silicon nitride is formed as an etching stopper between the gate electrode and the gate insulating film or between the substrate and the layer on the substrate, so that the over-etching can be prevented and the flatness of the eiement can be improved. In addition, a contact is formed in no consideration of the concept "contact hole".
Inventors
- 👤 Shunpei Yamazaki
- 👤 Hongyong Zhang
- 👤 Yasuhiko Takamura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 11:09
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0314; H10D30/0321; H10D30/60; H10D30/67; H10D30/6729; H10D30/673; H10D30/6731; H10D30/6737; H10D30/6739; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6745; H10D30/6746; H10D86/00; H10D86/40; H10D86/441; H10D86/60; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/069; G; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/1333; G02F1/1345; G02F1/13454; G02F1/136; G02F1/1362; G02F1/13624; G02F1/136245
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
145 words
An insulated gate thin film transistor comprising: a semiconductor layer formed on an insulating surface having source, drain and channel regions therein; a first insulating layer provided on said semiconductor layer; a second insulating layer located over said channel region with said first insulating layer therebetween, said second insulating layer having opposed side edges; a gate electrode located over said channel region with said first insulating layer and said second insulating layer interposed therebetween; and an anodic oxide coating covering a surface of said gate electrode, said oxide coating being formed by anodic oxidizing a surface of said gate electrode, wherein said first insulating layer extends beyond said side edges of the second insulating layer to cover a major surface of said source and drain regions and said side edges of the second insulating layer are approximately coextensive with edges of said anodic oxide coating.
Claim 2
Dependent Claim
145 words
An insulated gate thin film transistor comprising: a semiconductor layer formed on an insulating surface having source, drain and channel regions therein; a first insulating layer provided on said semiconductor layer; a second insulating layer located over said channel region with said first insulating layer therebetween, said second insulating layer having opposed side edges; a gate electrode located over said channel region with said first insulating layer and said second insulating layer interposed therebetween; and an anodic oxide coating covering a surface of said gate electrode, said oxide coating being formed by anodic oxidizing a surface of said gate electrode, wherein said first insulating layer extends beyond said side edges of the second insulating layer to cover a major surface of said source and drain regions and said side edges of the second insulating layer are approximately coextensive with edges of said anodic oxide coating.
Claim 3
Dependent Claim
31 words
The transistor of claim 1 wherein said side edges of said second insulating layer approximately correspond to boundaries between said source and channel regions and between said drain and channel regions.
Claim 4
Dependent Claim
107 words
An insulated gate field effect transistor comprising: a semiconductor layer formed on an insulating surface having source, drain and channel regions therein; a first insulating layer provided on said semiconductor layer; a second insulating layer laminated on said first insulating layer; a gate electrode located over said channel region with said first insulating layer and said second insulating layer interposed therebetween; and an anodic oxide coating formed on said gate electrode, wherein a boundary between said source and channel regions and a boundary between said drain and channel regions are each approximately aligned with side edges of both said first insulating layer and said second insulating layer.
Claim 5
Dependent Claim
107 words
An insulated gate field effect transistor comprising: a semiconductor layer formed on an insulating surface having source, drain and channel regions therein; a first insulating layer provided on said semiconductor layer; a second insulating layer laminated on said first insulating layer; a gate electrode located over said channel region with said first insulating layer and said second insulating layer interposed therebetween; and an anodic oxide coating formed on said gate electrode, wherein a boundary between said source and channel regions and a boundary between said drain and channel regions are each approximately aligned with side edges of both said first insulating layer and said second insulating layer.
Claim 6
Dependent Claim
31 words
The transistor of claim 3 wherein said side edges of both said first insulating layer and said second insulating layer are substantially aligned with side edges of said anodic oxide coating.
Claim 7
Dependent Claim
101 words
An insulated gate thin film transistor comprising: a semiconductor layer formed on an insulating surface having source, drain and channel regions therein; a first insulating layer provided on said semiconductor layer; a second insulating layer located over said channel region with said first insulating layer therebetween, said second insulating layer having opposed side edges; a gate electrode located over said channel region with said first insulating layer and said second insulating layer interposed therebetween, wherein said first insulating layer extends beyond said side edges of the second insulating layer to cover a major upper surface of said source and drain regions.
Claim 8
Dependent Claim
101 words
An insulated gate thin film transistor comprising: a semiconductor layer formed on an insulating surface having source, drain and channel regions therein; a first insulating layer provided on said semiconductor layer; a second insulating layer located over said channel region with said first insulating layer therebetween, said second insulating layer having opposed side edges; a gate electrode located over said channel region with said first insulating layer and said second insulating layer interposed therebetween, wherein said first insulating layer extends beyond said side edges of the second insulating layer to cover a major upper surface of said source and drain regions.
Claim 9
Dependent Claim
32 words
The transistor of claim 5 Wherein said side edges of said second insulating layer approximately correspond to boundaries between said source and channel regions and between said drain and channel regions, respectively.
Claim 10
Dependent Claim
26 words
The transistor of claim 5 wherein said first insulating layer is provided with at least one contact hole on one of said source and drain regions.
Claim 11
Dependent Claim
89 words
An insulated gate field effect transistor comprising: a semiconductor layer formed on an insulating surface having source, drain and channel regions therein; a first insulating layer provided on said semiconductor layer; a second insulating layer located over said channel region with said first insulating layer therebetween; a gate electrode located over said channel region with said first insulating layer and said second insulating layer interposed therebetween, wherein both of said first insulating layer and said second insulating layer cover an upper surface of said source, drain and channel regions.
Claim 12
Dependent Claim
89 words
An insulated gate field effect transistor comprising: a semiconductor layer formed on an insulating surface having source, drain and channel regions therein; a first insulating layer provided on said semiconductor layer; a second insulating layer located over said channel region with said first insulating layer therebetween; a gate electrode located over said channel region with said first insulating layer and said second insulating layer interposed therebetween, wherein both of said first insulating layer and said second insulating layer cover an upper surface of said source, drain and channel regions.
Claim 13
Dependent Claim
28 words
The transistor of claim 8 wherein at least one contact hole is provided for one of said source and drain regions through said first and second insulating layer.
Claim 14
Dependent Claim
25 words
The insulated gate thin film transistor of claim 5 or 8 wherein said first insulating layer comprises a different material from said second insulating material.
Claim 15
Dependent Claim
36 words
The transistor of claim 5 or 8 wherein said first insulating layer and said second insulating layer each comprises a material selected from the group consisting of aluminum oxide, silicon nitride, silicon oxide and phosphosilicate glass.
Claim 16
Dependent Claim
26 words
The transistor of claim 5 or 8 wherein said first insulating layer comprises silicon oxide while said second insulating layer comprises altoninure oxide or silicon oxide.
Claim 17
Dependent Claim
21 words
The transistor of claim 5 or 8 wherein said second insulating layer has a higher conductivity than said first insulating layer.
Claim 18
Dependent Claim
27 words
The transistor of claim 5 or 8 wherein said gate electrode is covered with an oxide coating formed by anodic oxidizing a surface of said gate electrode.
Claim 19
Dependent Claim
80 words
An insulated gate thin film transistor comprising: a semiconductor layer having source, drain and channel regions therein; a first insulating layer contacting said semiconductor layer; a second insulating layer laminated on said first insulating layer; a gate electrode provided adjacent to said channel region with said first insulating layer and said second insulating layer interposed therebetween; and an anodic oxide coating formed on said gate electrode, wherein said second insulating layer has a higher conductivity than said first insulating layer.
Claim 20
Dependent Claim
80 words
An insulated gate thin film transistor comprising: a semiconductor layer having source, drain and channel regions therein; a first insulating layer contacting said semiconductor layer; a second insulating layer laminated on said first insulating layer; a gate electrode provided adjacent to said channel region with said first insulating layer and said second insulating layer interposed therebetween; and an anodic oxide coating formed on said gate electrode, wherein said second insulating layer has a higher conductivity than said first insulating layer.
Claim 21
Dependent Claim
13 words
The transistor of claim 15 wherein said first insulating layer comprises silicon oxide.
Claim 22
Dependent Claim
27 words
The transistor of claim 16 wherein said second insulating layer comprises a silicon nitride where the proportion of nitrogen with respect to silicon is 1 to 4/3.
References Cited (Backward Citations)
US4015281A
Cited
US4042945A
Cited
US4015781A
Cited
US4485393A
Cited
US4866498A
Cited
US5051794A
Cited
JPH0338278A
Cited
US5041888A
Cited
US5177577A
Cited
US5225356A
Cited
US5289030A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-11-20 | 1999-05-22 | 1999-11-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-11-20 | 2003-05-22 | 2003-11-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-11-20 | 2007-05-22 | 2007-11-21 | $7700.00 | Window Closed / Lapsed |