Low voltage EEPROM

Claim 2

A non-volatile memory system comprising: a memory cell array including a P conductivity type substrate; an N well of an N conductivity type formed in the substrate; a P well of the P conductivity type formed in the N well; a group of memory cells disposed in the P well and arranged in an array having a multiplicity of rows and columns, each of said cells including (a) a drain region of the N conductivity type; (b) a source region of the N conductivity type, spaced apart from the drain region so as to define a channel region in the P well intermediate the source and drain regions; (c) a floating gate disposed over the channel region and insulated from the channel region; (d) a control gate disposed over the floating gate and insulated from the floating gate; and control means for applying voltages to the cells of the array so as to program, read and erase the cells, said control means including read means for reading a selected one of the cells by applying a reference voltage to the substrate, a first voltage, having a negative polarity with respect to the reference voltage, to the source region of the selected cell, a second voltage, having a positive polarity with respect to the reference voltage, to the drain region of the selected cell, and a third voltage, having a positive polarity with respect to the reference voltage, to the control gate of the selected cell, and wherein the cells have an erased threshold voltage when erased with a magnitude which is greater than that of the first voltage.

Claim 3

The memory system of claim 1 wherein the read means also functions to apply a fourth voltage, having a negative polarity with respect to the reference voltage, to the P well.

Claim 4

The memory system of claim 2 wherein the read means also functions to apply the reference voltage to the N well.

Claim 5

The memory system of claim 3 wherein the first and fourth voltages have the same magnitude.

Claim 6

The memory system of claim 1 wherein the P well and the N well define a PN junction therebetween and wherein the read means applies voltages to the P well and N well such that the PN junction is reversed biased.

Claim 7

The memory system of claim 1 wherein the control means further includes erase means for erasing the cells of the array by applying the reference voltage to the substrate, a fifth voltage, having a positive polarity with respect to the reference voltage, to the P well and a sixth voltage, having a negative polarity with respect to the reference voltage, to the control gate of the cells.

Claim 8

The memory system of claim 6 wherein the N well and the P substrate define a PN junction and wherein the erase means applies voltages to the N well and the P substrate such that the PN junction is reversed biased.

Claim 9

The memory system of claim 7 wherein the erase means causes the fifth voltage to be applied to the N well.

Claim 10

A non-volatile memory system comprising: a memory cell array including a first conductivity type semiconductor body; a first well of a second conductivity type, opposite the first conductivity type, formed in the body; a second well of the first conductivity type formed in the first well, with first and second well forming a PN junction at an interface between the wells; a group of memory cells disposed in the second well and arranged in an array having a multiplicity of rows and columns, each of said cells including (a) a drain region of the second conductivity type; (b) a source region of the second conductivity type, spaced apart from the drain region, so as to define a channel region in the second well intermediate the source and drain regions; (c) a floating gate disposed over the channel region and insulated from the channel region; (d) a control gate disposed over the floating gate and insulated from the floating gate; and control means for applying voltages to the cells of the array so as to program, read and erase the cells, said control means including read means for reading a selected one of the cells by applying a reference voltage to the body, a first voltage, having a first polarity with respect to the reference voltage, to the source region of the selected cell, a second voltage, of a second polarity opposite the first polarity, with respect to the reference voltage, to the drain region of the selected cell, and a third voltage, having the second polarity, with respect to the reference voltage, to the control gate of the selected cell and wherein the read means further applies voltages to the first and second wells so as to reverse bias the PN junction; and erase means for erasing the cells of the array by applying the reference voltage to the body, and applying a voltage having the first polarity, with respect to the reference voltage, to the second well and a voltage having the second polarity, with respect to the reference voltage, to the control gate of the cells to be erased.

Claim 11

A non-volatile memory system comprising: a memory cell array including a first conductivity type semiconductor body; a first well of a second conductivity type, opposite the first conductivity type, formed in the body; a second well of the first conductivity type formed in the first well, with first and second well forming a PN junction at an interface between the wells; a group of memory cells disposed in the second well and arranged in an array having a multiplicity of rows and columns, each of said cells including (a) a drain region of the second conductivity type; (b) a source region of the second conductivity type, spaced apart from the drain region, so as to define a channel region in the second well intermediate the source and drain regions; (c) a floating gate disposed over the channel region and insulated from the channel region; (d) a control gate disposed over the floating gate and insulated from the floating gate; and control means for applying voltages to the cells of the array so as to program, read and erase the cells, said control means including read means for reading a selected one of the cells by applying a reference voltage to the body, a first voltage, having a first polarity with respect to the reference voltage, to the source region of the selected cell, a second voltage, of a second polarity opposite the first polarity, with respect to the reference voltage, to the drain region of the selected cell, and a third voltage, having the second polarity, with respect to the reference voltage, to the control gate of the selected cell and wherein the read means further applies voltages to the first and second wells so as to reverse bias the PN junction; and erase means for erasing the cells of the array by applying the reference voltage to the body, and applying a voltage having the first polarity, with respect to the reference voltage, to the second well and a voltage having the second polarity, with respect to the reference voltage, to the control gate of the cells to be erased.

Claim 12

The memory system of claim 9 wherein the cells, when erased, have an erased threshold voltage with a magnitude which is greater than that of the first voltage.

Claim 13

The system of claim 9 wherein the body and the first well form another PN junction at an interface of the body and the first well and wherein the erase means applies voltages to the first well and the body so that the another PN junction is reversed biased.

Claim 14

The system of claim 11 wherein the first conductivity type is P type and the second conductivity type is N type.