US5457647A
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Passive hierarchical bitline memory architecture which resides in metal layers of a SRAM array
Assignee: STMicroelectronics lnc USA
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Filing: 1993-03-31
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Granted: 1995-10-10
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Expires: 2013-03-31
Abstract
Abstract In a high density memory, such as a SRAM, DRAM, EPROM or EEPROM, a hierarchical bitline configuration is utilized such that a number of local bitlines are connected to a master bitline through interface circuitry which connects a local bitline to the master bitline. Local select signals, when set to the appropriate voltage level, couple a local bitline to the master bitline. In addition to reducing the local bitline capacitance that must be driven by memory cells, the hierarchical configuration may provide layout area savings as well.
Inventors
- 👤 David C. McClure
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 02:31
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/18; G11C7/12
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
111 words
A partitioned static random access memory (SRAM) array, comprising: a plurality of master bitlines which reside in a first metal layer of the partitioned SRAM array; a plurality of local bitlines, which reside in a second metal layer of the partitioned SRAM array, connected to a plurality of memory cells, wherein each local bitline is connected to a loading element such that each bitline is tied to a predetermined voltage level; a plurality of interface circuits, which connects master bitline to at least two of the local bitlines; and a plurality of local select signals, each capable of selecting a corresponding local bitline to be coupled to its corresponding master bitline.
Claim 2
Dependent Claim
111 words
A partitioned static random access memory (SRAM) array, comprising: a plurality of master bitlines which reside in a first metal layer of the partitioned SRAM array; a plurality of local bitlines, which reside in a second metal layer of the partitioned SRAM array, connected to a plurality of memory cells, wherein each local bitline is connected to a loading element such that each bitline is tied to a predetermined voltage level; a plurality of interface circuits, which connects master bitline to at least two of the local bitlines; and a plurality of local select signals, each capable of selecting a corresponding local bitline to be coupled to its corresponding master bitline.
Claim 3
Dependent Claim
19 words
The memory array of claim 1, wherein each local select signal controls one interface circuit for each master bitline.
Claim 4
Dependent Claim
16 words
The memory array of claim 1, wherein the interface circuitry is comprised of a n-channel transistor.
Claim 5
Dependent Claim
20 words
The memory array of claim 3, wherein the gate of the n-channel transistor is connected to a local select signal.
Claim 6
Dependent Claim
18 words
The memory array of claim 3, wherein the local select signals are bootstrapped above a first supply voltage.
Claim 7
Dependent Claim
15 words
The memory array of claim 5, wherein the first supply voltage is V cc .
Claim 8
Dependent Claim
24 words
The memory array of claim 3, wherein the n-channel transistor has a lower V T such that the voltage drop across it is minimized.
Claim 9
Dependent Claim
29 words
The memory array of claim 3, wherein a well in which the n-channel transistor resides is pumped to a lower voltage which is less than a second supply voltage.
Claim 10
Dependent Claim
15 words
The memory array of claim 8, wherein the second supply voltage is V SS .
Claim 11
Dependent Claim
26 words
The memory array of claim 1, wherein the interface circuitry is comprised of a full CMOS transmission gate having a n-channel transistor and a p-channel transistor.
Claim 12
Dependent Claim
37 words
The memory array of claim 10, wherein the gate of the n-channel transistor is connected to a local select signal and the gate of the p-channel transistor is connected to the complement of the local select signal.
Claim 13
Dependent Claim
15 words
The memory array of claim 1, wherein the loading element is a high value resistor.
Claim 14
Dependent Claim
17 words
The memory array of claim 12, wherein the high value resistor is formed in a polysilicon layer.
Claim 15
Dependent Claim
18 words
The memory array of claim 13, wherein the high value resistor is formed in an active diffusion region.
Claim 16
Dependent Claim
15 words
The memory array of claim 1, wherein the loading element is a pull up transistor.
Claim 17
Dependent Claim
26 words
The memory array of claim 1, wherein the memory array is formed using a first metal layer, a second metal layer, and a third metal layer.
Claim 18
Dependent Claim
18 words
The memory array of claim 16, wherein the master bitlines are formed on top of the local bitlines.
Claim 19
Dependent Claim
19 words
The memory array of claim 16, where the master bitlines are formed at an offset from the local bitlines.
Claim 20
Dependent Claim
27 words
The memory array of claim 1, wherein the first metal layer which contains the master bitlines is above the second metal layer which contains the local bitlines.
Claim 21
Dependent Claim
24 words
The memory array of claim 12, wherein each local bitline is a local bitline pair and each master bitline is a master bitline pair.
Claim 22
Dependent Claim
37 words
The memory array of claim 20, wherein the partitioned SRAM array is a 4 Megabit SRAM which is comprised of four local bitline pairs connected to a master bitline pair, each bitline pair having 128 memory cells.
Claim 23
Dependent Claim
15 words
The 4 Megabit SRAM of claim 21, wherein the interface circuitry is an n-channel transistor.
Claim 24
Dependent Claim
30 words
The memory array of claim 1, wherein one of the local bitlines may be recovered when its local select signal is selected while its corresponding master bitline is being recovered.
Claim 25
Dependent Claim
21 words
The memory array of claim 1, wherein each local bitline has an equilibrate device which is controlled by an equilibration signal.
Claim 26
Dependent Claim
19 words
The memory array of claim 24, wherein the equilibration signal is decoded based on its corresponding local select signal.
Claim 27
Dependent Claim
21 words
The memory array of claim 1, wherein each local bitline has a precharge device which is controlled by a precharge signal.
Claim 28
Dependent Claim
19 words
The memory array of claim 26, wherein the precharge signal is decoded based on its corresponding local select signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-10-09 | 1999-04-10 | 1999-10-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-10-09 | 2003-04-10 | 2003-10-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-10-09 | 2007-04-10 | 2007-10-10 | $7700.00 | Window Closed / Lapsed |