US4131951A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed complementary MOS memory
Assignee: Toshiba Corp
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Filing: 1977-05-17
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Granted: 1978-12-26
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Expires: 1997-05-17
Abstract
Abstract A complementary MOS memory with improved access time is provided with a speed-up signal level changing circuit having two bus lines in which the signal level of the bus line on which a signal level is changing is detected dependent on the signal level difference between the bus lines and the signal level on the bus line with the changing signal level is rapidly changed to the full value of the signal level change, and a switching circuit for coupling the speed-up signal level changing circuit with a reference potential level. In the complementary MOS memory, the signal level appearing on the bus line with the changing signal level is forced to change to be the reference potential level every access cycle, through the operations of the speed-up signal level changing circuit and the switching circuit.
Inventors
- 👤 Hiroji Asahi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 19:43
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/419; G11C11/412
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
213 words
A high speed complementary MOS memory comprising: first and second data bus lines and row selection lines; a plurality of memory cells provided between said first and second data bus lines and connected to said row selection lines; precharge means connected to said first and second bus lines for precharging said bus lines to an initial level every access cycle, said precharge means including resistive means tending to maintain said bus lines at said initial level; sensing means connected to one of said bus lines for detecting read out data dependent on a change of the signal level on the bus line connected thereto; data writing means connected to said bus lines for supplying write data to said bus lines to set the voltage level thereon to a predetermined level; speed-up signal level changing means connected between said first and second bus lines for detecting signal level change in either bus line on the basis of a signal level difference between said bus lines and for rapidly changing the signal level on the bus lines on which a signal level change is detected to a reference signal level potential; and switching means connected to said speed-up signal level changing means for coupling said signal level changing means to said reference signal level potential.
Claim 2
Dependent Claim
213 words
A high speed complementary MOS memory comprising: first and second data bus lines and row selection lines; a plurality of memory cells provided between said first and second data bus lines and connected to said row selection lines; precharge means connected to said first and second bus lines for precharging said bus lines to an initial level every access cycle, said precharge means including resistive means tending to maintain said bus lines at said initial level; sensing means connected to one of said bus lines for detecting read out data dependent on a change of the signal level on the bus line connected thereto; data writing means connected to said bus lines for supplying write data to said bus lines to set the voltage level thereon to a predetermined level; speed-up signal level changing means connected between said first and second bus lines for detecting signal level change in either bus line on the basis of a signal level difference between said bus lines and for rapidly changing the signal level on the bus lines on which a signal level change is detected to a reference signal level potential; and switching means connected to said speed-up signal level changing means for coupling said signal level changing means to said reference signal level potential.
Claim 3
Dependent Claim
65 words
A high speed complementary MOS memory according to claim 1 in which said data writing means comprises MOS-FETs of specific channel type of which the gates are commonly connected to a column selection line, and these MOS-FETs are conductive when the memory is addressed and permit at this time given write data fed from a data input circuit to be supplied to said bus lines.
Claim 4
Dependent Claim
72 words
A high speed complementary MOS memory according to claim 1, in which said precharge means comprises first and second MOS-FETs of specific channel type operating in response to a chip enable signal and said resistive means includes first and second resistors with given values of resistrance sufficient to sustain said initial level in said bus lines, these first and second resistors being connected in parallel respectively to said first and second MOS-FETs.
Claim 5
Dependent Claim
72 words
A high speed complementary MOS memory according to claim 1, in which said speed-up signal level changing means comprises a flip-flop circuit including first and second MOS-FETs of a given channel type, the gates of said first and second MOS-FETs being cross-connected to said bus lines, said flip-flop circuit being rapidly set in a predetermined conduction state in response to a change of the signal level on one of said bus lines.
Claim 6
Dependent Claim
58 words
A high speed complementary MOS memory according to claim 1, in which said switching means comprises a MOS-FET of given channel type which is conductive when the gate of said MOS-FET receives a switch signal delayed until the signal level on said bus lines reaches the potential level enough to stably drive said speed-up signal level changing means.
Claim 7
Dependent Claim
73 words
A high speed complementary MOS memory according to claim 1, in which said sensing means includes first and second MOS-FETs connected to each other in series fashion, the gate of said first MOS-FET being connected to one of said bus lines while the gate of said second MOS-FET being connected to the column selection line, and said sensing means detects the data read out of the memory cell located at a given address.
Claim 8
Dependent Claim
49 words
A high speed complementary MOS memory according to claim 1, in which said signal level changing means is a flip-flop comprising first and second complementary MOS circuits of given channel type, and said precharge means comprises MOS-FETs of given channel type operating in response to a chip enable signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-12-25 | 1982-06-26 | 1982-12-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-12-25 | 1986-06-26 | 1986-12-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-12-25 | 1990-06-26 | 1990-12-26 | $7700.00 | Window Closed / Lapsed |