US3978459A
Expired / Lapsed
US
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High density mos memory array
Assignee: Intel Corp
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Filing: 1975-04-21
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Granted: 1976-08-31
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Expires: 1995-04-21
Abstract
Abstract A high density MOS integrated circuit memory array utilizing single device dynamic cells and a uniquely controlled sense amplifier. The loads of the sense amplifier are also used to precharge bit lines thereby reducing the number of devices used in prior art arrays. A single noise suppression circuit provides planar noise suppression, the circuit is clocked with the same signals used to control the sense amplifier.
Inventors
- 👤 James T. Koo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 16:03
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356017; H03K3/356052; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4091; H03K3/356086; H03K3/356095
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
95 words
In an MOS dynamic RAM employing a plurality of sense lines coupled to a plurality of sense amplifiers an improvement comprising: at least a first transistor in each of said sense amplifiers, coupled between a source of potential and said sense line; and signal generation means coupled to said sense amplifiers for causing said first transistor in each of said sense amplifiers to sequentially charge said sense line and operate as a load in said sense amplifier; whereby a single transistor performs both a precharging function and operate as a load in the sense amplifier.
Claim 2
Dependent Claim
95 words
In an MOS dynamic RAM employing a plurality of sense lines coupled to a plurality of sense amplifiers an improvement comprising: at least a first transistor in each of said sense amplifiers, coupled between a source of potential and said sense line; and signal generation means coupled to said sense amplifiers for causing said first transistor in each of said sense amplifiers to sequentially charge said sense line and operate as a load in said sense amplifier; whereby a single transistor performs both a precharging function and operate as a load in the sense amplifier.
Claim 3
Dependent Claim
17 words
The improvement defined by claim 1 wherein said signal generation means includes a plurality of delay circuits.
Claim 4
Dependent Claim
40 words
The improvement defined by claim 2 wherein said sense amplifier includes a second transistor, coupled to said first transistor which selectively couples said first transistor such that current flows through said first and second transistors from said source of potential.
Claim 5
Dependent Claim
34 words
The improvement defined by claim 3 wherein said second transistor is controlled by a control signal, and wherein said control signal is applied to one of said delay circuits of said signal generation means.
Claim 6
Dependent Claim
15 words
The improvement defined by claim 4 wherein said first and second transistors comprise n-channel devices.
Claim 7
Dependent Claim
23 words
the improvement defined by claim 5 wherein said first and second transistors and said signal generation means are fabricated on a common substrate.
Claim 8
Dependent Claim
82 words
In an MOS dynamic memory employing a plurality of sense lines coupled to a plurality of sense amplifiers wherein each of said sense amplifiers include a bistable circuit having a first and a second load transistor each coupled between a source of potential and one of such sense lines, an improvement comprising: control means coupled to such sense amplifiers for causing such first and second transistors to selectively charge such sense lines and alternately to operate as loads in such sense amplifiers.
Claim 9
Dependent Claim
82 words
In an MOS dynamic memory employing a plurality of sense lines coupled to a plurality of sense amplifiers wherein each of said sense amplifiers include a bistable circuit having a first and a second load transistor each coupled between a source of potential and one of such sense lines, an improvement comprising: control means coupled to such sense amplifiers for causing such first and second transistors to selectively charge such sense lines and alternately to operate as loads in such sense amplifiers.
Claim 10
Dependent Claim
33 words
The improvement defined by claim 7 including a third transistor in such sense amplifiers for selectively permitting current to flow in such sense amplifiers from said source of potential thereby activating such amplifiers.
Claim 11
Dependent Claim
45 words
The improvement defined by claim 8 wherein said control means causes said third transistor to conduct prior to the time that such first and second transistors conduct such that the loads in such sense amplifiers are the nonconducting impedence of such first and second transistors.
Claim 12
Dependent Claim
16 words
The improvement defined by claim 9 wherein said control means includes a plurality of delay circuits.
Claim 13
Dependent Claim
33 words
The improvement defined by claim 10 wherein such memory, such first and second transistors, said third transistor and said control means employ n-channel transistors which are disposed on a common p-type silicon substrate.
Claim 14
Dependent Claim
40 words
The improvement defined by claim 8 wherein such memory includes a plurality of word lines and wherein said word lines are selectively clamped to a second potential through a circuit means, said circuit means being coupled to said control means.
Claim 15
Dependent Claim
27 words
The improvement defined by claim 12 wherein said word lines are decoupled from said second potential when such first and second transistors and said third transistor conduct.
Claim 16
Dependent Claim
17 words
The improvement defined by claim 13 wherein said second potential is the potential of the memory ground.
Claim 17
Dependent Claim
94 words
In an MOS memory employing a plurality of sense amplifiers and a plurality of word lines, an improvement for suppressing noise in such memory comprising: circuit means for selectively coupling such word lines in such memory to a common potential and for decoupling such word lines in such memory from said common potential when such sense amplifiers are activated; and control means for generating a control signal for controlling said circuit means, coupled to said circuit means; whereby said circuit means suppresses noise in such memory associated with, or transmitted by, such word lines.
Claim 18
Dependent Claim
94 words
In an MOS memory employing a plurality of sense amplifiers and a plurality of word lines, an improvement for suppressing noise in such memory comprising: circuit means for selectively coupling such word lines in such memory to a common potential and for decoupling such word lines in such memory from said common potential when such sense amplifiers are activated; and control means for generating a control signal for controlling said circuit means, coupled to said circuit means; whereby said circuit means suppresses noise in such memory associated with, or transmitted by, such word lines.
References Cited (Backward Citations)
US3769621A
Cited
US3806898A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-08-31 | 1980-03-01 | 1980-08-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-08-31 | 1984-03-01 | 1984-08-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-08-31 | 1988-03-01 | 1988-08-31 | $7700.00 | Window Closed / Lapsed |