US5343433A
Expired / Lapsed
US
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CMOS sense amplifier
Assignee: Texas Instruments Inc
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Filing: 1990-07-26
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Granted: 1994-08-30
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Expires: 2010-07-26
Abstract
Abstract A CMOS sense amplifier circuit for a dynamic read/write memory employs cross-coupled N-channel transistors and cross-coupled P-channel transistors, returned to the voltage supply and ground through transistors activated by sense clocks. The differential inputs of the sense amplifier are connected to the bit lines through coupling transistors which are held on when the word line and dummy line go high, then are shut off while the sense amplifier is activated by the sense clocks; the coupling transistors are then turned on for selected columns before being turned on for non-selected columns. The current needed to charge and discharge the bit lines is thus spread out, and the peak current is decreased.
Inventors
- 👤 Charvaka Duvvury
- 👤 Adin E. Hyslop
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 02:32
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4091; G11C7/00; G11C7/06; G11C7/065; G11C7/12
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
328 words
A CMOS amplifier circuit for a memory device comprising: a pair of bit lines, and a plurality of dynamic memory cells separately connected to each of said pair of bit lines, a cross-coupled flip-flop circuit including a first pair of N-channel transistors and a second pair of P-channel transistors, each transistor having a source-to-drain path and a gate, the source-to-drain paths of the first pair of transistors connected between a pair of sense nodes and a grounding node, the source-to-drain paths of the second pair of P-channel transistors connected between said sense nodes and a voltage supply node, a pair of coupling transistors having source-to-drain paths separately connecting said pair of sense nodes to said pair of bit lines, and having gates connected to control circuitry, a third pair of N-channel transistors each having a source-to-drain path and a gate, the source-to-drain paths of the third pair of N-channel transistors being connected in parallel between said grounding node and a ground terminal of a voltage supply, the gates of said third pair of N-channel transistors being connected to said control circuitry, a P-channel pull-up transistor having a source-to-drain path connecting said voltage supply node to a positive voltage supply, and having a gate connected to said control circuitry, said control circuitry applying activating voltages in sequence to said gates of said third pair of N-channel transistors, and applying an activating voltage to said gate of said P-channel pull-up transistor, and applying an activating voltage to said gates of said coupling transistors in an active cycle during a time period that said memory cells are activated for coupling to said bit lines, then applying a deactivating voltage of substantially zero to said gates of said coupling transistors in said active cycle during a time period that at least one of said gates of said third pair of N-channel transistors is activated by said control circuitry, and thereafter applying an activating voltage again to said gates of the coupling transistors.
Claim 2
Dependent Claim
328 words
A CMOS amplifier circuit for a memory device comprising: a pair of bit lines, and a plurality of dynamic memory cells separately connected to each of said pair of bit lines, a cross-coupled flip-flop circuit including a first pair of N-channel transistors and a second pair of P-channel transistors, each transistor having a source-to-drain path and a gate, the source-to-drain paths of the first pair of transistors connected between a pair of sense nodes and a grounding node, the source-to-drain paths of the second pair of P-channel transistors connected between said sense nodes and a voltage supply node, a pair of coupling transistors having source-to-drain paths separately connecting said pair of sense nodes to said pair of bit lines, and having gates connected to control circuitry, a third pair of N-channel transistors each having a source-to-drain path and a gate, the source-to-drain paths of the third pair of N-channel transistors being connected in parallel between said grounding node and a ground terminal of a voltage supply, the gates of said third pair of N-channel transistors being connected to said control circuitry, a P-channel pull-up transistor having a source-to-drain path connecting said voltage supply node to a positive voltage supply, and having a gate connected to said control circuitry, said control circuitry applying activating voltages in sequence to said gates of said third pair of N-channel transistors, and applying an activating voltage to said gate of said P-channel pull-up transistor, and applying an activating voltage to said gates of said coupling transistors in an active cycle during a time period that said memory cells are activated for coupling to said bit lines, then applying a deactivating voltage of substantially zero to said gates of said coupling transistors in said active cycle during a time period that at least one of said gates of said third pair of N-channel transistors is activated by said control circuitry, and thereafter applying an activating voltage again to said gates of the coupling transistors.
Claim 3
Dependent Claim
14 words
A circuit according to claim 1 wherein said pair of coupling transistors are N-channel.
Claim 4
Dependent Claim
37 words
A circuit according to claim 1 wherein said control circuitry activates the gates of said coupling transistors at a variable time delay after said grounding means are activated, depending upon an address applied to said memory device.
Claim 5
Dependent Claim
17 words
A circuit according to claim 1 wherein said memory cells are one-transistor dynamic MOS read/write memory cells.
Claim 6
Dependent Claim
191 words
In a semiconductor memory having at least two blocks of memory cells, each of said cells of each of said blocks selectively storing an electric charge, each block having a set of sense amplifiers, each sense amplifier connected to a line of memory cells in its block to selectively amplify the charge stored in individual memory cells in its line of memory cells, switch means in the connections between each sense amplifier and its line of memory cells to temporarily disconnect each sense amplifier from its line of memory cells during an amplification operation and then to reconnect each sense amplifier to its line of memory cells, the switch means including a selectible time control that effects the reconnection in the cell block containing a selected cell before the reconnection in the other blocks of memory cells, in which the sense amplifier has a power supply connection, and a clock circuit is connected to open said power supply connection before the switch means disconnects the cell line, to then close the power supply connection while the cell line is still disconnected, and to subsequently cause the reconnection of the cell lines,
Claim 7
Dependent Claim
191 words
In a semiconductor memory having at least two blocks of memory cells, each of said cells of each of said blocks selectively storing an electric charge, each block having a set of sense amplifiers, each sense amplifier connected to a line of memory cells in its block to selectively amplify the charge stored in individual memory cells in its line of memory cells, switch means in the connections between each sense amplifier and its line of memory cells to temporarily disconnect each sense amplifier from its line of memory cells during an amplification operation and then to reconnect each sense amplifier to its line of memory cells, the switch means including a selectible time control that effects the reconnection in the cell block containing a selected cell before the reconnection in the other blocks of memory cells, in which the sense amplifier has a power supply connection, and a clock circuit is connected to open said power supply connection before the switch means disconnects the cell line, to then close the power supply connection while the cell line is still disconnected, and to subsequently cause the reconnection of the cell lines,
Claim 8
Dependent Claim
82 words
The combination of claim 5 in which there is a clock generator connected to supply cycles of different timing pulses, one such pulse being timed to initiate a cell line disconnect in all the memory blocks, and a set of later pulses each to a different cell block, said set initiation being responsive to a cell designation signal to first initiate cell line reconnects in the block having the designated cell, and later to initiate cell line reconnects in the remaining blocks.
Claim 9
Dependent Claim
51 words
The combination of claim 5 in which the memory has more than two blocks of memory cells and the selectable time control is constructed to separately reconnect the sense amplifiers of the different blocks to their sets of memory cell lines, and to effect each block reconnect at a different time.
Claim 10
Dependent Claim
42 words
The combination of claim 5 in which the memory is constructed for operation by an electric potential of a given supply voltage but the switch means is constructed to effect its switching with a switching potential of above said given supply voltage.
Claim 11
Dependent Claim
335 words
A CMOS sense amplifier circuit for a dynamic memory device, comprising: a pair of bit lines, and a plurality of dynamic memory cells separately connected to each of said pair of bit lines, a cross-coupled flip-flop circuit including a first pair of N-channel transistors and a second pair of P-channel transistors, each transistor having a source-to-drain path and a gate, the source-to-drain paths of the first pair of N-channel transistors connected between a pair of sense nodes and a grounding node, the source-to-drain paths of the second pair of P-channel transistors connected between said sense nodes and a positive voltage supply node, said gates of the first pair of N-channel transistors and the second pair of P-channel transistors being cross-coupled to said pair of sense nodes, said sense nodes being coupled to said pair of bit lines, a third pair of N-channel transistors each having a source-to-drain path and a gate, the source-to-drain paths of said third pair of transistors being connected in parallel between said grounding node and a ground terminal of a voltage supply, one of said third pair being smaller than the other, a P-channel pull-up transistor having a source-to-drain path and a gate, the source-to-drain path of the pull-up transistor being connected between said positive voltage supply node and a positive terminal of said voltage supply, and control circuitry connected to said gates of said third pair of N-channel transistors and to said gate of said P-channel pull-up transistor to apply activating voltages to said gates during an active cycle, said control circuitry applying an activating voltage to the gate of said one of said third pair at a given time in said active cycle while a selected one of said memory cells is activated for coupling to a bit line and to one of said sense nodes, said control circuitry applying activating voltages to the gates of the other of said third pair and to said gate of said P-channel pull-up transistor in said active cycle after said given time.
Claim 12
Dependent Claim
335 words
A CMOS sense amplifier circuit for a dynamic memory device, comprising: a pair of bit lines, and a plurality of dynamic memory cells separately connected to each of said pair of bit lines, a cross-coupled flip-flop circuit including a first pair of N-channel transistors and a second pair of P-channel transistors, each transistor having a source-to-drain path and a gate, the source-to-drain paths of the first pair of N-channel transistors connected between a pair of sense nodes and a grounding node, the source-to-drain paths of the second pair of P-channel transistors connected between said sense nodes and a positive voltage supply node, said gates of the first pair of N-channel transistors and the second pair of P-channel transistors being cross-coupled to said pair of sense nodes, said sense nodes being coupled to said pair of bit lines, a third pair of N-channel transistors each having a source-to-drain path and a gate, the source-to-drain paths of said third pair of transistors being connected in parallel between said grounding node and a ground terminal of a voltage supply, one of said third pair being smaller than the other, a P-channel pull-up transistor having a source-to-drain path and a gate, the source-to-drain path of the pull-up transistor being connected between said positive voltage supply node and a positive terminal of said voltage supply, and control circuitry connected to said gates of said third pair of N-channel transistors and to said gate of said P-channel pull-up transistor to apply activating voltages to said gates during an active cycle, said control circuitry applying an activating voltage to the gate of said one of said third pair at a given time in said active cycle while a selected one of said memory cells is activated for coupling to a bit line and to one of said sense nodes, said control circuitry applying activating voltages to the gates of the other of said third pair and to said gate of said P-channel pull-up transistor in said active cycle after said given time.
Claim 13
Dependent Claim
77 words
A sense amplifier circuit according to claim 9 wherein said sense nodes are coupled to said pair of bit lines by source-to-drain paths of a fourth pair of N-channel transistors, and gates of said fourth pair are connected to said control circuitry to receive an activating voltage which is at a zero level to render said fourth pair non-conductive for a time period in the active cycle after said given time and conductive following said time period.
Claim 14
Dependent Claim
39 words
A sense amplifier according to claim 10 wherein said time period includes the time that said activating voltages are applied to the gates of said other of said third pair and to the gate of said P-channel pull-up transistor.
Claim 15
Dependent Claim
39 words
A sense amplifier circuit according to claim 9 wherein said activating voltage applied to the gate of said P-channel pull-up transistor is obtained by inverting said activating voltage applied to the gate of said other of said third pair.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-29 | 1998-02-28 | 1998-08-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-29 | 2002-02-28 | 2002-08-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-29 | 2006-02-28 | 2006-08-30 | $7700.00 | Window Closed / Lapsed |