Dynamic random access memory having improved layout and method of arranging memory cells of the dynamic random access memory

Claim 1

A method of arranging memory cells of a dynamic random access memory, the memory including a semiconductor substrate having a plurality of active regions, each memory cell including an active region having a first impurity diffusion region, a second impurity diffusion region in common with an adjacent memory cell and a channel forming region located between the first and second impurity diffusion regions, the first impurity diffusion regions of adjacent active regions being located at positions symmetrical with respect to the common second impurity diffusion region; a plurality of uniformly spaced word lines; a plurality of uniformly spaced bit lines being orthogonal to the word lines, each bit line having a protrusion; a plurality of stacked capacitors each having a storage electrode; and an insulation layer having a plurality of first contact holes each electrically connecting the storage electrode of each stacked capacitor and each corresponding first impurity diffusion region and a plurality of second contact holes each electrically connecting each bit line and each corresponding second impurity diffusion region; the method comprising the steps of: selecting the position of each bit line protrusion as the position of each second impurity diffusion region in each corresponding active region; determining the position of the first impurity diffusion region in one of two adjacent active regions so that it corresponds to a position spaced away from the center line of the corresponding bit line protrusion in a longitudinal direction of the memory cell, at a predetermined distance and a predetermined angle; determining the position of the first impurity diffusion region in the other of two adjacent active regions so that it corresponds to a position that is symmetrical with the position of the first impurity diffusion region with respect to the center line of the corresponding bit line protrusion; determining the center of each first contact hole and the center of each second contact hole to correspond to the center of each first impurity diffusion region and the center of each second impurity diffusion region, respectively, and determining the size of each first contact hole and the size of each corresponding second contact hole so that the two contact holes are positioned a predetermined distance away from the word lines and bit lines arranged adjacent thereto; and determining the center of the stacked capacitor so that it corresponds to the center of each corresponding first contact hole, thereby determining the position of each stacked capacitor in a region defined by two adjacent word lines and two adjacent bit lines.

Claim 2

A method of arranging memory cells of a dynamic random access memory, the memory including a semiconductor substrate having a plurality of active regions, each memory cell including an active region having a first impurity diffusion region, a second impurity diffusion region in common with an adjacent memory cell and a channel forming region located between the first and second impurity diffusion regions, the first impurity diffusion regions of adjacent active regions being located at positions symmetrical with respect to the common second impurity diffusion region; a plurality of uniformly spaced word lines; a plurality of uniformly spaced bit lines being orthogonal to the word lines, each bit line having a protrusion; a plurality of stacked capacitors each having a storage electrode; and an insulation layer having a plurality of first contact holes each electrically connecting the storage electrode of each stacked capacitor and each corresponding first impurity diffusion region and a plurality of second contact holes each electrically connecting each bit line and each corresponding second impurity diffusion region; the method comprising the steps of: selecting the position of each bit line protrusion as the position of each second impurity diffusion region in each corresponding active region; determining the position of the first impurity diffusion region in one of two adjacent active regions so that it corresponds to a position spaced away from the center line of the corresponding bit line protrusion in a longitudinal direction of the memory cell, at a predetermined distance and a predetermined angle; determining the position of the first impurity diffusion region in the other of two adjacent active regions so that it corresponds to a position that is symmetrical with the position of the first impurity diffusion region with respect to the center line of the corresponding bit line protrusion; determining the center of each first contact hole and the center of each second contact hole to correspond to the center of each first impurity diffusion region and the center of each second impurity diffusion region, respectively, and determining the size of each first contact hole and the size of each corresponding second contact hole so that the two contact holes are positioned a predetermined distance away from the word lines and bit lines arranged adjacent thereto; and determining the center of the stacked capacitor so that it corresponds to the center of each corresponding first contact hole, thereby determining the position of each stacked capacitor in a region defined by two adjacent word lines and two adjacent bit lines.