Dynamic random access memory having improved layout and method of arranging memory cell pattern of the dynamic random access memory

Claim 2

A dynamic random access memory comprising: a semiconductor substrate having an active region including first and second diffusion regions of a transfer transistor; an insulating layer formed on said semiconductor substrate and having first and second contact holes; a stacked capacitor having a storage electrode which is electrically coupled to said first diffusion region through said first contact hole formed in said insulating layer and an opposed electrode; a word line electrically isolated from said semiconductor substrate; and a bit line electrically isolated from said semiconductor substrate and electrically coupled to said second diffusion region through said second contact hole formed in said insulating layer, said second contact hole being approximately positioned at a center (CL) of said bit line, and said word line having a bent portion located between said first and second contact holes so that said word line is separated from said second contact hole at a predetermined distance.

Claim 3

A dynamic random access memory as claimed in claim 1, wherein said bent portion of the word line is arranged so that said bent portion is orthogonal to an imaginary line which connects a center of said first contact hole and a center of said second contact hole.

Claim 4

A dynamic random access memory as claimed in claim 1, wherein said active region is obliquely arranged with respect to said bit line and said word line.

Claim 5

A dynamic random access memory as claimed in claim 2, wherein said active region is arranged along said imaginary line.

Claim 6

A dynamic random access memory as claimed in claim 1, wherein said bent portion of the word line has an arc-shaped pattern.

Claim 7

A dynamic random access memory as claimed in claim 1, wherein: said bent portion of the word line has a first area, a second area and a third area which are integrally formed in this order; said second area is orthogonal to said bit line; and one of said first and second areas is orthogonal to an imaginary line which connects a center of said first contact hole and a center of said second contact hole.

Claim 8

A dynamic random access memory as claimed in claim 6, wherein said first and third areas are arranged in symmetry with each other about said second

Claim 9

A dynamic random access memory as claimed in claim 1, wherein said active region comprises a bent active portion extending toward said bit line.

Claim 10

A dynamic random access memory as claimed in claim 1, wherein said active region comprises a bent active portion which is bent at a center of said first contact hole and which extends toward said bit line.

Claim 11

A dynamic random access memory as claimed in claim 9, wherein: said active region comprises a straight portion integrally formed with said bent active portion thereof; and said bent active portion of the active region is partially in symmetry with said straight portion about said center of the first contact hole.

Claim 12

A dynamic random access memory as claimed in claim 8, wherein said bent active portion of the active region has an end which is located below said bit line.

Claim 13

A dynamic random access memory as claimed in claim 8, wherein said bent active portion of the active region is obliquely arranged with respect to said bit line.

Claim 14

A dynamic random access memory as claimed in claim 1, wherein: an imaginary line which connects a center of said first contact hole and a center of said second contact hole is inclined at an angle θ with respect to a direction in which said bit line extends; and said angle θ is defined substantially as follows: θ= sin.sup.-1 (1/2b+e+c)/(a+c+d+2e)] where a: half a width of the second contact hole, e: an alignment margin of each of said first and second contact holes, d: a width of the word line, c: half a width of said first contact hole, and b: a width of said bit line.

Claim 15

A dynamic random access memory as claimed in claim 1, wherein said first and second contact holes are substantially of circular shapes.

Claim 16

A dynamic random access memory as claimed in claim 1, wherein said first diffusion region is a drain region and said second diffusion region is a source region.

Claim 17

A dynamic random access memory as claimed in claim 1, wherein said bit line is formed at a layer level lower than that of said opposed electrode.

Claim 18

A dynamic random access memory comprising: a semiconductor substrate having a plurality of active regions, each including first and second diffusion regions of a transfer transistor; an insulating layer formed on said semiconductor substrate and having a plurality of first contact holes and a plurality of second contact holes; a plurality of stacked capacitors, each having a storage electrode which is electrically coupled to a corresponding one of the first diffusion regions through a corresponding one of the first contact holes formed in said insulating layer and an opposed electrode; a plurality of word lines electrically isolated from said semiconductor substrate; and a plurality of bit lines electrically isolated from said semiconductor substrate, each of said bit lines being electrically coupled to a corresponding one of said second diffusion regions through a corresponding one of the second contact holes formed in said insulating layer, each of said second contact holes being approximately positioned at a center of a corresponding one of the bit lines, and each of said word lines having a bent portion located between a corresponding one of the first contact holes and a corresponding one of the second contact holes so that a corresponding one of the word lines is separated from said corresponding one of the second contact holes at a predetermined distance.

Claim 19

A dynamic random access memory comprising: a semiconductor substrate having a plurality of active regions, each including first and second diffusion regions of a transfer transistor; an insulating layer formed on said semiconductor substrate and having a plurality of first contact holes and a plurality of second contact holes; a plurality of stacked capacitors, each having a storage electrode which is electrically coupled to a corresponding one of the first diffusion regions through a corresponding one of the first contact holes formed in said insulating layer and an opposed electrode; a plurality of word lines electrically isolated from said semiconductor substrate; and a plurality of bit lines electrically isolated from said semiconductor substrate, each of said bit lines being electrically coupled to a corresponding one of said second diffusion regions through a corresponding one of the second contact holes formed in said insulating layer, each of said second contact holes being approximately positioned at a center of a corresponding one of the bit lines, and each of said word lines having a bent portion located between a corresponding one of the first contact holes and a corresponding one of the second contact holes so that a corresponding one of the word lines is separated from said corresponding one of the second contact holes at a predetermined distance.

Claim 20

A dynamic random access memory as claimed in claim 17, wherein: each of said first contact holes is located at an almost equal distance from two adjacent word lines from among said plurality of word lines; each of said first contact holes is located at an almost equal distance from two adjacent bit lines from among said plurality of bit lines.

Claim 21

A dynamic random access memory as claimed in claim 17, wherein said bent portion of each of the word lines is arranged so that said bent portion is orthogonal to an imaginary line which connects a center of said corresponding one of the first contact holes and a center of said corresponding one of the second contact holes.

Claim 22

A dynamic random access memory as claimed in claim 17, wherein each of said active regions is obliquely arranged with respect to said bit lines and said word lines.

Claim 23

A dynamic random access memory as claimed in claim 19, wherein each of said active regions is arranged along said imaginary line.

Claim 24

A dynamic random access memory as claimed in claim 17, wherein said bent portion of each of the word lines has an arc-shaped pattern.

Claim 25

A dynamic random access memory as claimed in claim 17, wherein each of said active regions comprises a bent active portion extending toward a corresponding one of the bit lines.

Claim 26

A dynamic random access memory as claimed in claim 17, wherein each of said active regions comprises a bent active portion which is bent at a center of a corresponding one of the first contact holes and which extends toward a corresponding one of the bit lines.

Claim 27

A dynamic random access memory as claimed in claim 24, wherein: each of said active regions comprises a straight portion integrally formed with said bent active portion thereof; and said bent active portion of each of the active regions is partially in symmetry with said straight portion about said center of said corresponding one of the first contact holes.

Claim 28

A dynamic random access memory as claimed in claim 23, wherein said bent active portion of each of said active regions has an end which is located below a corresponding one of the bit lines.

Claim 29

A dynamic random access memory as claimed in claim 23, wherein said bent active portion of each of said active regions is obliquely arranged with respect to a corresponding one of the bit lines.

Claim 30

A dynamic random access memory claimed in claim 17, wherein: an imaginary line which connects a center of said corresponding one of the first contact holes and a center of said corresponding one of the second contact holes is inclined at an angle θ with respect to a direction in which said bit lines extend; and said angle θ is defined substantially as follows: θ=sin .sup.-1 ((1/2b+e+c)/(a+c+d+2e)] where a: half a width of each of the second contact holes, e: an alignment margin of each of said plurality of first and second contact holes, d: a width of the word lines, c: half a width of said first contact holes, and b: a width of said bit lines.

Claim 31

A dynamic random access memory as claimed in claim 17, wherein said pluralities of first and second contact holes are substantially of circular shapes.

Claim 32

A dynamic random access memory as claimed in claim 17, wherein each of said bit lines is formed at a layer level lower than that of each of said opposed electrodes.

Claim 33

A dynamic random access memory as claimed in claim 17, wherein said bit lines are of a folded-bit line type.

Claim 36

A method as claimed in claim 32, wherein: said first predetermined distance is approximately equal to b/2+c+e where b is a width of said bit line, c is half a width of said first contact hole, d is a width of the word line, and e is an alignment margin of said first contact hole; said second predetermined distance is approximately equal to a+c+d+2e where a is a half a width of said second contact hole.

Claim 39

A method as claimed in claim 34, wherein: said predetermined angle θ is defined substantially as follows: θ= sin.sup.-1 (1/2b+e+c)/(a+c+d+2e)] where a: half a width of said second contact hole, e: an alignment margin of each of said first and second contact holes, d: a width of said word line, c: half a width of said first contact hole, and b: a width of said bit line; and said predetermined distance is approximately equal to b/2+c+e.