Reduced power VLSI chip and driver circuit

Claim 2

A CMOS off-chip driver circuit having a reduced power dissipation, comprising: a data input terminal and a control signal input terminal coupled to pre-drive circuitry; a first node coupled to said pre-drive circuitry and coupled to a gate electrode of a first n-channel FET, said first node associated with said data input terminal; a second node coupled to said pre-drive circuitry, said second node associated with said control signal input terminal; a second n-channel FET coupled between a first voltage supply and an output terminal, a p-well node of said second n-channel FET coupled to a source electrode of said second n-channel FET; a third n-channel FET coupled between said output terminal and a second voltage supply, said second node coupled to a gate electrode of said third n-channel FET; a p-channel FET coupled in series with a first resistor between said first voltage supply and a third node coupled to a gate electrode of said second n-channel FET; and a fourth n-channel FET coupled in series with a second resistor between said third node and said second voltage supply, a p-well node of said fourth n-channel FET coupled to a source electrode of said fourth n-channel FET, wherein said first node is coupled to a gate electrode of said p-channel FET and said first n-channel FET is coupled between said third node and said second voltage supply.

Claim 3

A driver circuit comprising: means for receiving an input data signal having a voltage swing of a first magnitude; and means, coupled to said receiving means, for outputting an output data signal to an output terminal, said output data signal corresponding to said input data signal, said output data signal having a voltage swing of a second magnitude wherein said second magnitude is less than said first magnitude, said outputting means including: a pull-up transistor coupled in series with a pull-down transistor between first and second voltage sources of given magnitudes; said output terminal coupled to a junction coupling said pull-up transistor to said pull-down transistor; and means, coupled to said output terminal, for regulating a control voltage applied to a gate electrode of said pull-up transistor in order to produce said output data signal at said output terminal having a voltage swing of said second magnitude, wherein said second magnitude is less than said first magnitude, and wherein said regulating means includes: a first FET coupled in series with a first resistor between said first voltage source and said gate electrode of said pull-up transistor; a second FET coupled in series with a second resistor between said gate electrode of said pull-up transistor and said second voltage source, wherein a gate electrode of said second FET is coupled to said output terminal; and a third FET coupled between said gate electrode of said pull-up transistor and said second voltage source, wherein a gate electrode of said third FET is coupled to a gate electrode of said first FET and an input terminal, and wherein a gate electrode of said pull-down transistor is coupled to a control input.

Claim 4

A driver circuit comprising: means for receiving an input data signal having a voltage swing of a first magnitude; and means, coupled to said receiving means, for outputting an output data signal to an output terminal, said output data signal corresponding to said input data signal, said output data signal having a voltage swing of a second magnitude wherein said second magnitude is less than said first magnitude, said outputting means including: a pull-up transistor coupled in series with a pull-down transistor between first and second voltage sources of given magnitudes; said output terminal coupled to a junction coupling said pull-up transistor to said pull-down transistor; and means, coupled to said output terminal, for regulating a control voltage applied to a gate electrode of said pull-up transistor in order to produce said output data signal at said output terminal having a voltage swing of said second magnitude, wherein said second magnitude is less than said first magnitude, and wherein said regulating means includes: a first FET coupled in series with a first resistor between said first voltage source and said gate electrode of said pull-up transistor; a second FET coupled in series with a second resistor between said gate electrode of said pull-up transistor and said second voltage source, wherein a gate electrode of said second FET is coupled to said output terminal; and a third FET coupled between said gate electrode of said pull-up transistor and said second voltage source, wherein a gate electrode of said third FET is coupled to a gate electrode of said first FET and an input terminal, and wherein a gate electrode of said pull-down transistor is coupled to a control input.