US4626711A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Exclusive or gate circuit
Assignee: National Semiconductor Corp
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Filing: 1984-05-11
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Granted: 1986-12-02
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Expires: 2004-05-11
Abstract
Abstract An exclusive-or circuit which is extremely fast, uses lower power and fewer components, and is easier to manufacture than prior art circuits is achieved in a circuit which uses only a single reference voltage potential (shown as positive) in the portion of the circuit which generates exclusive-nor logic, and uses a feedback transistor to prevent saturation of a switching transistor. In the off state of the switching transistor, the single reference potential causes the base to be several saturation potentials above ground. In the on state, the feedback transistor reduces the base current. Thus the voltage swing between on and off states is less than in prior art circuits. In addition, the logic from many input signals can be combined to create a single exclusive-nor signal before buffering to an exclusive-or signal at the output terminal.
Inventors
- 👤 Gabriel M. Li
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 21:12
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/013; H03K17/00; H03K17/04; H03K17/042; H03K17/0422; H03K19/20; H03K19/21; H03K19/212
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
322 words
An exclusive-or gate circuit comprising: an exclusive-nor gate logic circuit having at least first and second input terminals and an output node; and an inverter gate circuit having an input terminal coupled to said output node of said exclusive-nor logic circuit, whereby said inverter gate produces an output that represents the exclusive-nor function of said first and second input terminals, wherein said exclusive-nor logic circuit comprises: first, second, third, and fourth transistors, each having emitter, base, and collector electrodes; means coupling the emitter of said first transistor to said first input terminal; means coupling said base of said first transistor to a first voltage source; means coupling said collector of said first transistor to said base of said third transistor and to said emitter of said fourth transistor; means coupling said emitter of said second transistor to said second input terminal; means coupling said base of said second transistor to said first voltage source; means coupling said collector of said second transistor to said base of said fourth transistor and to said emitter of said third transistor; and means coupling said collectors of said third and fourth transistors together to comprise said exclusive-nor logic circuit output and to load means for coupling said output to said first voltage source; said load means comprise fifth and sixth transistors, each one having emitter, base and collector electrodes; means coupling said emitter of said fifth transistor, through a series resistor, to said exclusive-nor logic circuit output node; means coupling said collector of said fifth transistor to said first voltage source; means coupling said base of said sixth transistor to said exclusive-nor logic circuit output node; means including a resistor voltage divider having a tap, coupled between said collector of said sixth transistor and said first voltage source; and means coupling said base of said fifth transistor to said tap on said resistor voltage divider whereby said exclusive-or gate circuit includes a speed up feedback circuit.
Claim 2
Dependent Claim
322 words
An exclusive-or gate circuit comprising: an exclusive-nor gate logic circuit having at least first and second input terminals and an output node; and an inverter gate circuit having an input terminal coupled to said output node of said exclusive-nor logic circuit, whereby said inverter gate produces an output that represents the exclusive-nor function of said first and second input terminals, wherein said exclusive-nor logic circuit comprises: first, second, third, and fourth transistors, each having emitter, base, and collector electrodes; means coupling the emitter of said first transistor to said first input terminal; means coupling said base of said first transistor to a first voltage source; means coupling said collector of said first transistor to said base of said third transistor and to said emitter of said fourth transistor; means coupling said emitter of said second transistor to said second input terminal; means coupling said base of said second transistor to said first voltage source; means coupling said collector of said second transistor to said base of said fourth transistor and to said emitter of said third transistor; and means coupling said collectors of said third and fourth transistors together to comprise said exclusive-nor logic circuit output and to load means for coupling said output to said first voltage source; said load means comprise fifth and sixth transistors, each one having emitter, base and collector electrodes; means coupling said emitter of said fifth transistor, through a series resistor, to said exclusive-nor logic circuit output node; means coupling said collector of said fifth transistor to said first voltage source; means coupling said base of said sixth transistor to said exclusive-nor logic circuit output node; means including a resistor voltage divider having a tap, coupled between said collector of said sixth transistor and said first voltage source; and means coupling said base of said fifth transistor to said tap on said resistor voltage divider whereby said exclusive-or gate circuit includes a speed up feedback circuit.
Claim 3
Dependent Claim
123 words
The exclusive-or gate circuit of claim 1 further comprising: seventh and eighth transistors each one having emitter, base and collector electrodes; means coupling said emitter of said seventh transistor to said inverter gate output; means coupling said collector of said seventh transistor to said first voltage source; means coupling said base of said seventh transistor to said collector of said sixth transistor; means coupling said collector of said eighth transistor to said inverter gate output; means coupling said emitter of said eighth transistor to a second voltage source; and means coupling said base of said eighth transistor to said emitter of said sixth transistor whereby said seventh and eighth transistors comprise pull up and pull down elements respectively of said inverter gate circuit.
Claim 4
Dependent Claim
51 words
The exclusive-or gate circuit of claim 2 further comprising a plurality of series connected diodes coupled between said second voltage source and said base of said seventh transistor, said diodes being poled to conduct the current supplied by said first voltage source, whereby the signal swing of said circuit is limited.
Claim 5
Dependent Claim
32 words
The exclusive-or gate circuit of claim 3 wherein at least one diode of said plurality is a Schottky diode and said first, second, third, fourth, sixth and eighth transistors are Schottky transistors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-12-01 | 1990-06-02 | 1990-12-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-12-01 | 1994-06-02 | 1994-12-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-12-01 | 1998-06-02 | 1998-12-02 | $7700.00 | Window Closed / Lapsed |