US4355246A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Transistor-transistor logic circuit
Assignee: Fujitsu Ltd
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Filing: 1978-12-08
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Granted: 1982-10-19
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Expires: 1998-12-08
Abstract
Abstract A delay element is introduced into a transistor-transistor logic circuit having a totem-pole-connected inverter transistor and an off-buffer transistor, in order to ensure a safe and correct operation even in the case where the transistor-transistor logic circuit is used as an element of multiple-connected transistor-transistor logic circuits.
Inventors
- 👤 Yuzo Usui
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 01:28
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00307; H03K19/0008; H03K19/001
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
193 words
A three-state transistor-transistor logic circuit that is operable without a control input, said logic circuit comprising: an input stage for inputting a signal to said TTL circuit, a phase-split transistor stage connected to receive the output of said input stage, a totem-pole-connected circuit including an off-buffer transistor connected serially with an inverter transistor, the bases of said off-buffer and inverter transistors being connected to respective points of said phase-split transistor stage, a delay circuit having its output connected to the base of said off-buffer transistor and its input selectively connected to the input of said input stage or to a respective terminal of said phase-split transistor stage, said connection of said input and output of the delay circuit providing a low level output of said TTL circuit when the input to said TTL circuit is at a high level a high level output for a period equal to the delay time of said delay circuit, after said high level input returns to a low level input, and an open state output of the TTL circuit at other times, wherein said TTL circuit is operable without said control input to produce said three outputs.
Claim 2
Dependent Claim
193 words
A three-state transistor-transistor logic circuit that is operable without a control input, said logic circuit comprising: an input stage for inputting a signal to said TTL circuit, a phase-split transistor stage connected to receive the output of said input stage, a totem-pole-connected circuit including an off-buffer transistor connected serially with an inverter transistor, the bases of said off-buffer and inverter transistors being connected to respective points of said phase-split transistor stage, a delay circuit having its output connected to the base of said off-buffer transistor and its input selectively connected to the input of said input stage or to a respective terminal of said phase-split transistor stage, said connection of said input and output of the delay circuit providing a low level output of said TTL circuit when the input to said TTL circuit is at a high level a high level output for a period equal to the delay time of said delay circuit, after said high level input returns to a low level input, and an open state output of the TTL circuit at other times, wherein said TTL circuit is operable without said control input to produce said three outputs.
Claim 3
Dependent Claim
60 words
The TTL circuit of claim 1 said phase-split transistor stage comprising a phase-split transistor having its emitter connected to the base of said inverter transistor and its collector connected to the base of said off-buffer transistor, and said delay circuit having its input connected to the input of said input stage for receiving said input signal to said TTL circuit.
Claim 4
Dependent Claim
19 words
The TTL circuit of claim 2, said delay circuit having the characteristic of transmitting a signal without polarity reversal.
Claim 5
Dependent Claim
35 words
The TTL circuit of claim 3, said delay circuit comprising four transistor stages and a diode connected between the output of the last of the four transistor stages and said output of the delay circuit.
Claim 6
Dependent Claim
32 words
The TTL circuit of claim 3, said delay circuit comprising three transistor stages, the output of the last of the three stages being connected directly to said output of the delay circuit.
Claim 7
Dependent Claim
34 words
The TTL circuit of claim 3, said delay circuit comprising two transistor stages and a diode connected between the output of the last of the two stages and said output of the delay circuit.
Claim 8
Dependent Claim
84 words
The TTL circuit of claim 1, said phase-split transistor stage comprising first and second transistors, said first transistor having its emitter connected to the base of said inverter transistor, its collector connected to said input of the delay circuit, and its base connected to the output of said input stage of the TTL circuit, and said second transistor having its collector connected to the base of the off-buffer transistor, and its base connected to the output of said input stage of the TTL circuit.
Claim 9
Dependent Claim
19 words
The TTL circuit of claim 7, said delay circuit having the characteristic of transmitting a signal with polarity reversal.
Claim 10
Dependent Claim
15 words
The TTL circuit of claim 8, said delay circuit consisting of a single transistor stage.
Claim 11
Dependent Claim
13 words
The TTL circuit of claim 8, said delay circuit comprising two transistor stages.
Claim 12
Dependent Claim
25 words
The TTL circuit of claim 8, said input stage consisting of an input transistor and a resistor for biasing the base of the input transistor.
Claim 13
Dependent Claim
27 words
The TTL circuit of claim 1, 3 or 8, said input stage consisting of a diode and a resistor connected to the output side of the diode.
Claim 14
Dependent Claim
21 words
The TTL circuit of claim 1, 3 or 8, comprising a diode connected between said off-buffer transistor and said inverter transistor.
Claim 15
Dependent Claim
20 words
The TTL circuit of claim 1, 3 or 8, said off-buffer transistor being replaced by a Darlington-connected pair of transistors.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-10-18 | 1986-04-19 | 1986-10-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-10-18 | 1990-04-19 | 1990-10-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-10-18 | 1994-04-19 | 1994-10-19 | $7700.00 | Window Closed / Lapsed |