US4037115A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bipolar switching transistor using a Schottky diode clamp
Assignee: AT&T Inc
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Filing: 1976-06-25
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Granted: 1977-07-19
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Expires: 1996-06-25
Abstract
Abstract A transistor-transistor logic gate is described which uses a number of bipolar switching transistors clamped in several different ways. In particular to better adapt a bipolar switching transistor to high frequency, high temperature operation, the collectors of the various switching transistors are clamped in a variety of novel ways, each to achieve a collector voltage higher than that normally achieved by the conventional Schottky diode clamp connected between the base and collector.
Inventors
- 👤 Charles Meng-Yuan Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 15:55
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/088
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
304 words
A circuit arrangement comprising a first terminal to be maintained at a reference potential, a second terminal to be maintained at an operating potential, an input terminal to be supplied with an input signal, an output terminal at which an output signal will be developed, a first junction transistor, means for coupling the input terminal to the base of the first transistor, a first and a second Schottky back-to-back between the collector and base of the first transistor, means for resistively coupling the node between said two diodes to the second terminal, a second and a third junction transistor, the base of said second transistor connected to the collector of the first transistor and resistively coupled to the second terminal, the collector of said second transistor connected to the second terminal, the emitter of said second transistor being connected to the base of the third transistor and resistively coupled to the output terminal, the collector of said third transistor being resistively coupled to the second terminal, the emitter of said third transistor being connected to the output terminal, a third Schottky diode having its anode connected to the base of the second transistor and its cathode to the collector of the third transistor, a fourth Schottky transistor having its base resistively coupled to the emitter of the first transistor, its emitter connected to the first terminal, a fifth junction transistor having its emitter connected to the first terminal, its collector connected to the output terminal, and its base resistively coupled to the collector of the fourth transistor and resistively coupled to the emitter of the first transistor, and a fourth Schottky diode having its anode connected to the emitter of the first transistor and its cathode to the output terminal whereby it is resistively connected between the collector and base of the fifth transistor.
Claim 2
Dependent Claim
304 words
A circuit arrangement comprising a first terminal to be maintained at a reference potential, a second terminal to be maintained at an operating potential, an input terminal to be supplied with an input signal, an output terminal at which an output signal will be developed, a first junction transistor, means for coupling the input terminal to the base of the first transistor, a first and a second Schottky back-to-back between the collector and base of the first transistor, means for resistively coupling the node between said two diodes to the second terminal, a second and a third junction transistor, the base of said second transistor connected to the collector of the first transistor and resistively coupled to the second terminal, the collector of said second transistor connected to the second terminal, the emitter of said second transistor being connected to the base of the third transistor and resistively coupled to the output terminal, the collector of said third transistor being resistively coupled to the second terminal, the emitter of said third transistor being connected to the output terminal, a third Schottky diode having its anode connected to the base of the second transistor and its cathode to the collector of the third transistor, a fourth Schottky transistor having its base resistively coupled to the emitter of the first transistor, its emitter connected to the first terminal, a fifth junction transistor having its emitter connected to the first terminal, its collector connected to the output terminal, and its base resistively coupled to the collector of the fourth transistor and resistively coupled to the emitter of the first transistor, and a fourth Schottky diode having its anode connected to the emitter of the first transistor and its cathode to the output terminal whereby it is resistively connected between the collector and base of the fifth transistor.
Claim 3
Dependent Claim
32 words
A circuit arrangement in accordance with claim 1 further comprising a fifth Schottky diode having its anode connected to the output terminal and its cathode to the collector of the first transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-07-18 | 1981-01-17 | 1981-07-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-07-18 | 1985-01-17 | 1985-07-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-07-18 | 1989-01-17 | 1989-07-19 | $7700.00 | Window Closed / Lapsed |