Semiconductor memory

Claim 2

In a semiconductor memory comprising: a. at lEast one memory cell including 1. a pair of double-emitter transistors each having a collector, a base and first and second emitters, the collector of each one of said pair of transistors being connected to the base of the other, respectively, and the first emitters of said pair of transistors being connected together, 2. an emitter impedance element connected at one end thereof to the commonly connected first emitters of said pair of transistors, and 3. a pair of relatively high-valued impedance elements each connected at one end thereof to the collector of a respective one of the pair of transistors, respectively; b. a pair of digit lines for said memory cell connected to the second emitters of said pair of transistors, respectively; c. a source of a constant emitter bias voltage connected to the other end of said emitter impedance element; d. an address line for said memory cell; and e. a source of an address voltage connected to said address line, said address voltage presenting a high or a low level when the corresponding memory cell is to be selected or nonselected, respectively; the improvement which comprises: a switching transistor having a collector, a base and doubleemitters; and a pair of relatively low-valued impedance elements each having a relatively low-valued impedance with respect to that of said high-valued impedance elements and connected between one of the double-emitters of said switching transistor and the collector of one of said pair of transistors, respectively; the base of said switching transistor being connected to said address line, said address voltage of the high or the low level rendering said switching transistor conductive or nonconductive, respectively, so that the low-valued impedance elements are loaded in the collector circuits of said pair of transistors concurrently when the address voltage presents the high level.

Claim 3

an emitter impedance element connected at one end thereof to the commonly connected first emitters of said pair of transistors, and

Claim 4

an emitter impedance element connected at one end thereof to the commonly connected first emitters of said pair of transistors, and

Claim 5

The combination according to claim 1, wherein said high-valued impedance elements are resistors having respectively a relatively high-valued resistance, and said low-valued impedance elements are resistors having respectively a relatively low-valued resistance with respect to that of said high-valued impedance elements.

Claim 6

The combination according to claim 1 which further comprises a source of a constant collector bias voltage connected to the collector of said switching transistor.

Claim 7

a pair of relatively high-valued impedance elements each connected at one end thereof to the collector of a respective one of the pair of transistors, respectively; b. a pair of digit lines for said memory cell connected to the second emitters of said pair of transistors, respectively; c. a source of a constant emitter bias voltage connected to the other end of said emitter impedance element; d. an address line for said memory cell; and e. a source of an address voltage connected to said address line, said address voltage presenting a high or a low level when the corresponding memory cell is to be selected or non-selected, respectively; the improvement which comprises: a switching transistor having a collector, a base and double-emitters; and a pair of relatively low-valued impedance elements each having a relatively low-valued impedance with respect to that of said high-valued impedance elements and connected between one of the double-emitters of said switching transistor and the collector of one of said pair of transistors, respectively; the base of said switching transistor being connected to said address line, said address voltage of the high or the low level rendering said switching transistor conductive or non-conductive, respectively, so that the low-valued impedance elements are loaded in the collector circuits of said pair of transistors concurrently when the address voltage presents the high level.

Claim 8

a pair of relatively high-valued impedance elements each connected at one end thereof to the collector of a respective one of the pair of transistors, respectively; b. a pair of digit lines for said memory cell connected to the second emitters of said pair of transistors, respectively; c. a source of a constant emitter bias voltage connected to the other end of said emitter impedance element; d. an address line for said memory cell; and e. a source of an address voltage connected to said address line, said address voltage presenting a high or a low level when the corresponding memory cell is to be selected or non-selected, respectively; the improvement which comprises: a switching transistor having a collector, a base and double-emitters; and a pair of relatively low-valued impedance elements each having a relatively low-valued impedance with respect to that of said high-valued impedance elements and connected between one of the double-emitters of said switching transistor and the collector of one of said pair of transistors, respectively; the base of said switching transistor being connected to said address line, said address voltage of the high or the low level rendering said switching transistor conductive or non-conductive, respectively, so that the low-valued impedance elements are loaded in the collector circuits of said pair of transistors concurrently when the address voltage presents the high level.

Claim 9

The combination according to claim 3 which further comprises means for connecting the source of the constant collector bias voltage to the other ends of the high-valued impedance elements, respectively.

Claim 10

The combination according to claim 3 which further comprises means for connecting said address line to the other ends of said high-valued impedance elements, respectively.

Claim 11

An improvement in a semiconductor memory according to claim 1 which further comprises a coupling impedance element connected between the collectors of the pair of transistors for preventing said pair of transistors from saturation.

Claim 12

The improvement according to claim 6, wherein said coupling impedance element comprises a pair of Schottky barrier diodes connected in parallel with and in opposite conductive direction to each other.

Claim 13

A bipolar semiconductor memory cell comprising: a. a pair of double-emitter transistors each having collector and base electrodes and first and second emitter electrodes, the collector and base electrodes of each of said pair of transistors being directly cross-coupled to the base and collector electrodes of the other, respectively, the first emitter electrodes of said pair of transistors being connected together so that said pair of transistors attain bistable operation, the second emitter electrodes of said pair of transistors being connected with a pair of digit lines, respectively; b. an emitter resistor connected at one end thereof with the commonly connected first emitter electrodes and at the other end thereof with a terminal aT which a constant potential is applied; c. a pair of relatively high-valued resistance elements connected respectively with the collector electrodes of said pair of transistors, d. a double-emitter switching transistor having collector, base and two emitter electrodes; e. a pair of relatively low-valued resistance elements connected between the emitter electrodes of said switching transistor and the collector electrodes of said pair of transistors, respectively; f. address means for supplying to the base electrode of said switching transistor an address voltage having active and inactive states when the cell is to be selected and non-selected, respectively, the potentials of the address voltage in the active and inactive states being so selected as to render the switching transistor into on and off states of conduction, respectively, g. a first potential source connected with the other ends of said high-valued resistance elements; and h. a second potential source connected with the collector electrode of said switching transistor, so that the collector electrodes of said pair of transistors are supplied with a collector operation potential through the high-valued resistance elements when the cell is non-selected, or through the series circuits of the switching transistor and the low-valued resistance element, which series circuits are shunting the high-valued resistance elements, when the cell is selected.

Claim 14

A bipolar semiconductor memory cell comprising: a. a pair of double-emitter transistors each having collector and base electrodes and first and second emitter electrodes, the collector and base electrodes of each of said pair of transistors being directly cross-coupled to the base and collector electrodes of the other, respectively, the first emitter electrodes of said pair of transistors being connected together so that said pair of transistors attain bistable operation, the second emitter electrodes of said pair of transistors being connected with a pair of digit lines, respectively; b. an emitter resistor connected at one end thereof with the commonly connected first emitter electrodes and at the other end thereof with a terminal aT which a constant potential is applied; c. a pair of relatively high-valued resistance elements connected respectively with the collector electrodes of said pair of transistors, d. a double-emitter switching transistor having collector, base and two emitter electrodes; e. a pair of relatively low-valued resistance elements connected between the emitter electrodes of said switching transistor and the collector electrodes of said pair of transistors, respectively; f. address means for supplying to the base electrode of said switching transistor an address voltage having active and inactive states when the cell is to be selected and non-selected, respectively, the potentials of the address voltage in the active and inactive states being so selected as to render the switching transistor into on and off states of conduction, respectively, g. a first potential source connected with the other ends of said high-valued resistance elements; and h. a second potential source connected with the collector electrode of said switching transistor, so that the collector electrodes of said pair of transistors are supplied with a collector operation potential through the high-valued resistance elements when the cell is non-selected, or through the series circuits of the switching transistor and the low-valued resistance element, which series circuits are shunting the high-valued resistance elements, when the cell is selected.