US4965464A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Power amplifier circuit for integrated digital circuits
Assignee: Siemens AG
•
Filing: 1989-09-19
•
Granted: 1990-10-23
•
Expires: 2009-09-19
Abstract
Abstract Power amplifier circuit for integrated digital circuits that combines the low permanent current consumption of a NOF push-pull output stage with the well-defined high level of a NON-NOFF amplifier stage having external clamp diode. An optimization of the leading edge is additionally achieved by fast drive and transient overdrive. A preceding inverter reduces the input capacitance of the overall circuit.
Inventors
- 👤 Paul-Werner von Basse
- 👤 Jean-Marc Dortu
- 👤 Andrea Herlitzek
- 👤 Dieter Kohlert
- 👤 Ulrich Schaper
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 00:57
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/017; H03K19/01707; H03K19/01721; H03K19/003; H03K19/00369; H03K19/00384; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018535; H03K19/02; H03K19/08; H03K19/094; H03K19/0952; H03K5/00; H03K5/01; H03K5/08; H03K5/082; H03K5/086; H03K5/088
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
401 words
An amplifier circuit comprising: a first field effect transistor (T16), a second field effect transistor (T26), a third field effect transistor (T36), a fourth field effect transistor (T46), a fifth field effect transistor (T56), a sixth field effect transistor (T66), a seventh field effect transistor (T76) and an eighth field effect transistor (T86); the first field effect transistor (T16), the third field effect transistor (T36) and the fifth field effect transistor (T56) being NON (normally on) transistors; the second field effect transistor (T26), the fourth field effect transistor (T46), the sixth field effect transistor (T66), the seventh field effect transistor (T76) and the eighth field effect transistor (T86) being NOFF (normally off) transistors; drain terminals of the first field effect transistor (T16), of the third field effect transistor (T36), of the fifth field effect transistor (T56) and of the seventh field effect transistor (T76) connected to one another; source terminals of the second field effect transistor (T26), of the fourth field effect transistor (T46), of the sixth field effect transistor (T66) and of the eighth field effect transistor (T86) connected to one another; a source terminal of the first field effect transistor (T16) connected to a gate terminal of the first field effect transistor (T16), to a drain terminal of the second field effect transistor (T26), to a gate terminal of the fourth field effect transistor (T46), to a gate terminal of the sixth field effect transistor (T66) and to a gate terminal of the eighth field effect transistor (T86); a source terminal of the third field effect transistor (T36) connected to a gate terminal of the third field effect transistor (T36), to a drain terminal of the fourth field effect transistor (T46) and to a gate terminal of the fifth field effect transistor (T56); a source terminal of the fifth field effect transistor (T56) connected to a drain terminal of the sixth field effect transistor (T66) and to a gate terminal of the seventh field effect transistor (T76); a source terminal of the seventh field effect transistor (T76) connected to a drain terminal of the eighth field effect transistor (T86); a diode (D6) having a positive terminal and a negative terminal; the drain terminal of the eighth field effect transistor (T86) connected to the positive terminal of the diode (D6); and the source terminal of the eighth field effect transistor (T86) connected to the negative terminal of the diode (D6).
Claim 2
Dependent Claim
401 words
An amplifier circuit comprising: a first field effect transistor (T16), a second field effect transistor (T26), a third field effect transistor (T36), a fourth field effect transistor (T46), a fifth field effect transistor (T56), a sixth field effect transistor (T66), a seventh field effect transistor (T76) and an eighth field effect transistor (T86); the first field effect transistor (T16), the third field effect transistor (T36) and the fifth field effect transistor (T56) being NON (normally on) transistors; the second field effect transistor (T26), the fourth field effect transistor (T46), the sixth field effect transistor (T66), the seventh field effect transistor (T76) and the eighth field effect transistor (T86) being NOFF (normally off) transistors; drain terminals of the first field effect transistor (T16), of the third field effect transistor (T36), of the fifth field effect transistor (T56) and of the seventh field effect transistor (T76) connected to one another; source terminals of the second field effect transistor (T26), of the fourth field effect transistor (T46), of the sixth field effect transistor (T66) and of the eighth field effect transistor (T86) connected to one another; a source terminal of the first field effect transistor (T16) connected to a gate terminal of the first field effect transistor (T16), to a drain terminal of the second field effect transistor (T26), to a gate terminal of the fourth field effect transistor (T46), to a gate terminal of the sixth field effect transistor (T66) and to a gate terminal of the eighth field effect transistor (T86); a source terminal of the third field effect transistor (T36) connected to a gate terminal of the third field effect transistor (T36), to a drain terminal of the fourth field effect transistor (T46) and to a gate terminal of the fifth field effect transistor (T56); a source terminal of the fifth field effect transistor (T56) connected to a drain terminal of the sixth field effect transistor (T66) and to a gate terminal of the seventh field effect transistor (T76); a source terminal of the seventh field effect transistor (T76) connected to a drain terminal of the eighth field effect transistor (T86); a diode (D6) having a positive terminal and a negative terminal; the drain terminal of the eighth field effect transistor (T86) connected to the positive terminal of the diode (D6); and the source terminal of the eighth field effect transistor (T86) connected to the negative terminal of the diode (D6).
Claim 3
Dependent Claim
167 words
The amplifier circuit according to claim 1, wherein the amplifier circuit further comprises: a ninth field effect transistor (T95); a gate terminal of the ninth field effect transistor (T95) connected to the drain terminal of the sixth field effect transistor (T65); a drain terminal of the ninth field effect transistor (T95) connected to the gate terminal of the seventh field effect transistor (T75); a first diode (D5) having a positive terminal and a negative terminal and a second diode (D9) having a positive terminal and a negative terminal; a source terminal of the ninth field effect transistor (T95) connected to the positive terminal of the first diode (D5); the source terminal of the third field effect transistor (T35) connected to the positive terminal of the second diode (D9); the negative terminals of the first diode (D5) and of the second diode (D9) connected to one another; and the negative terminal of the first diode (D5) connected to the source terminal of the eighth field effect transistor (T85).
Claim 4
Dependent Claim
186 words
The amplifier circuit according to claim 2, wherein the amplifier circuit further comprises: a third diode (D30) having a positive terminal and a negative terminal; a tenth field effect transistor (T100) and an eleventh field effect transistor (T110); the positive terminal of the third diode (D30) connected to the negative terminal of the second diode (D10); the negative terminal of the third diode (D30) connected to the source terminal of the eighth field effect transistor (T80); a drain terminal of the tenth field effect transistor (T100) connected to the drain terminal of the seventh field effect transistor (T70); a source terminal of the tenth field effect transistor (T100) connected to a gate terminal of the tenth field effect transistor (T100), to a drain terminal of the eleventh field effect transistor (T110) and to the positive terminal of the third diode (D30); a source terminal of the eleventh field effect transistor (T110) connected to the source terminal of the eighth field effect transistor (T80); and a gate terminal of the eleventh field effect transistor (T110) connected to the drain terminal of the eighth field effect transistor (T80).
Claim 5
Dependent Claim
451 words
An amplifier circuit comprising: a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a fifth field effect transistor, a sixth field effect transistor, a seventh field effect transistor and an eighth field effect transistor; the first field effect transistor, the third field effect transistor and the fifth field effect transistor being NON (normally on) transistors; the second field effect transistor, the fourth field effect transistor, the sixth field effect transistor, the seventh field effect transistor and the eighth field effect transistor being NOFF (normally off transistors; drain terminals of the first field effect transistor, of the third field effect transistor, of the fifth field effect transistor and of the seventh field effect transistor connected to one another; source terminals of the second field effect transistor, of the fourth field effect transistor, of the sixth field effect transistor and of the eighth field effect transistor connected to one another; a source terminal of the first field effect transistor connected to a gate terminal of the first field effect transistor, to a drain terminal of the second field effect transistor, to a gate terminal of the fourth field effect transistor, to a gate terminal of the sixth field effect transistor and to a gate terminal of the eighth field effect transistor; a source terminal of the third field effect transistor connected to a gate terminal of the third field effect transistor, to a drain terminal of the fourth field effect transistor and to a gate terminal of the fifth field effect transistor; a source terminal of the fifth field effect transistor connected to a drain terminal of the sixth field effect transistor and to a gate terminal of the seventh field effect transistor; a source terminal of the seventh field effect transistor connected to a drain terminal of the eighth field effect transistor; a ninth field effect transistor; a gate terminal of the ninth field effect transistor connected to the drain terminal of the sixth field effect transistor; a drain terminal of the ninth field effect transistor connected to the gate terminal of the seventh field effect transistor; a first diode having a positive terminal and a negative terminal and a second diode having a positive terminal and a negative terminal; a source terminal of the ninth field effect transistor connected to the positive terminal of the first diode; the source terminal of the third field effect transistor connected to the positive terminal of the second diode; the negative terminals of the first diode and of the second diode connected to one another; and the negative terminal of the first diode connected to the source terminal of the eighth field effect transistor.
Claim 6
Dependent Claim
451 words
An amplifier circuit comprising: a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a fifth field effect transistor, a sixth field effect transistor, a seventh field effect transistor and an eighth field effect transistor; the first field effect transistor, the third field effect transistor and the fifth field effect transistor being NON (normally on) transistors; the second field effect transistor, the fourth field effect transistor, the sixth field effect transistor, the seventh field effect transistor and the eighth field effect transistor being NOFF (normally off transistors; drain terminals of the first field effect transistor, of the third field effect transistor, of the fifth field effect transistor and of the seventh field effect transistor connected to one another; source terminals of the second field effect transistor, of the fourth field effect transistor, of the sixth field effect transistor and of the eighth field effect transistor connected to one another; a source terminal of the first field effect transistor connected to a gate terminal of the first field effect transistor, to a drain terminal of the second field effect transistor, to a gate terminal of the fourth field effect transistor, to a gate terminal of the sixth field effect transistor and to a gate terminal of the eighth field effect transistor; a source terminal of the third field effect transistor connected to a gate terminal of the third field effect transistor, to a drain terminal of the fourth field effect transistor and to a gate terminal of the fifth field effect transistor; a source terminal of the fifth field effect transistor connected to a drain terminal of the sixth field effect transistor and to a gate terminal of the seventh field effect transistor; a source terminal of the seventh field effect transistor connected to a drain terminal of the eighth field effect transistor; a ninth field effect transistor; a gate terminal of the ninth field effect transistor connected to the drain terminal of the sixth field effect transistor; a drain terminal of the ninth field effect transistor connected to the gate terminal of the seventh field effect transistor; a first diode having a positive terminal and a negative terminal and a second diode having a positive terminal and a negative terminal; a source terminal of the ninth field effect transistor connected to the positive terminal of the first diode; the source terminal of the third field effect transistor connected to the positive terminal of the second diode; the negative terminals of the first diode and of the second diode connected to one another; and the negative terminal of the first diode connected to the source terminal of the eighth field effect transistor.
Claim 7
Dependent Claim
589 words
An amplifier circuit comprising: a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a fifth field effect transistor, a sixth field effect transistor, a seventh field effect transistor and an eighth field effect transistor; the first field effect transistor, the third field effect transistor and the fifth field effect transistor being NON (normally on) transistors; the second field effect transistor, the fourth field effect transistor, the sixth field effect transistor, the seventh field effect transistor and the eighth field effect transistor being NOFF (normally off) transistors; drain terminals of the first field effect transistor, of the third field effect transistor, of the fifth field effect transistor and of the seventh field effect transistor connected to one another; source terminals of the second field effect transistor, of the fourth field effect transistor, of the sixth field effect transistor and of the eighth field effect transistor connected to one another; a source terminal of the first field effect transistor connected to a gate terminal of the first field effect transistor, to a drain terminal of the second field effect transistor, to a gate terminal of the fourth field effect transistor, to a gate terminal of the sixth field effect transistor and to a gate terminal of the eighth field effect transistor; a source terminal of the third field effect transistor connected to a gate terminal of the third field effect transistor, to a drain terminal of the fourth field effect transistor and to a gate terminal of the fifth field effect transistor; a source terminal of the fifth field effect transistor connected to a drain terminal of the sixth field effect transistor and to a gate terminal of the seventh field effect transistor; a source terminal of the seventh field effect transistor connected to a drain terminal of the eighth field effect transistor; a ninth field effect transistor; a gate terminal of the ninth field effect transistor connected to the drain terminal of the sixth field effect transistor; a drain terminal of the ninth field effect transistor connected to the gate terminal of the seventh field effect transistor; a first diode having a positive terminal and a negative terminal and a second diode having a positive terminal and a negative terminal; a source terminal of the ninth field effect transistor connected to the positive terminal of the first diode; the source terminal of the third field effect transistor connected to the positive terminal of the second diode; the negative terminals of the first diode and of the second diode connected to one another; and a third diode having a positive terminal and a negative terminal; a tenth field effect transistor and an eleventh field effect transistor; the positive terminal of the third diode connected to the negative terminal of the second diode; the negative terminal of the third diode connected to the source terminal of the eighth field effect transistor; a drain terminal of the tenth field effect transistor connected to the drain terminal of the seventh field effect transistor; a source terminal of the tenth field effect transistor connected to a gate terminal of the tenth field effect transistor, to a drain terminal of the eleventh field effect transistor and to the positive terminal of the third diode; a source terminal of the eleventh field effect transistor connected to the source terminal of the eighth field effect transistor; and a gate terminal of the eleventh field effect transistor connected to the drain terminal of the eighth field effect transistor.
Claim 8
Dependent Claim
589 words
An amplifier circuit comprising: a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a fifth field effect transistor, a sixth field effect transistor, a seventh field effect transistor and an eighth field effect transistor; the first field effect transistor, the third field effect transistor and the fifth field effect transistor being NON (normally on) transistors; the second field effect transistor, the fourth field effect transistor, the sixth field effect transistor, the seventh field effect transistor and the eighth field effect transistor being NOFF (normally off) transistors; drain terminals of the first field effect transistor, of the third field effect transistor, of the fifth field effect transistor and of the seventh field effect transistor connected to one another; source terminals of the second field effect transistor, of the fourth field effect transistor, of the sixth field effect transistor and of the eighth field effect transistor connected to one another; a source terminal of the first field effect transistor connected to a gate terminal of the first field effect transistor, to a drain terminal of the second field effect transistor, to a gate terminal of the fourth field effect transistor, to a gate terminal of the sixth field effect transistor and to a gate terminal of the eighth field effect transistor; a source terminal of the third field effect transistor connected to a gate terminal of the third field effect transistor, to a drain terminal of the fourth field effect transistor and to a gate terminal of the fifth field effect transistor; a source terminal of the fifth field effect transistor connected to a drain terminal of the sixth field effect transistor and to a gate terminal of the seventh field effect transistor; a source terminal of the seventh field effect transistor connected to a drain terminal of the eighth field effect transistor; a ninth field effect transistor; a gate terminal of the ninth field effect transistor connected to the drain terminal of the sixth field effect transistor; a drain terminal of the ninth field effect transistor connected to the gate terminal of the seventh field effect transistor; a first diode having a positive terminal and a negative terminal and a second diode having a positive terminal and a negative terminal; a source terminal of the ninth field effect transistor connected to the positive terminal of the first diode; the source terminal of the third field effect transistor connected to the positive terminal of the second diode; the negative terminals of the first diode and of the second diode connected to one another; and a third diode having a positive terminal and a negative terminal; a tenth field effect transistor and an eleventh field effect transistor; the positive terminal of the third diode connected to the negative terminal of the second diode; the negative terminal of the third diode connected to the source terminal of the eighth field effect transistor; a drain terminal of the tenth field effect transistor connected to the drain terminal of the seventh field effect transistor; a source terminal of the tenth field effect transistor connected to a gate terminal of the tenth field effect transistor, to a drain terminal of the eleventh field effect transistor and to the positive terminal of the third diode; a source terminal of the eleventh field effect transistor connected to the source terminal of the eighth field effect transistor; and a gate terminal of the eleventh field effect transistor connected to the drain terminal of the eighth field effect transistor.
Claim 9
Dependent Claim
329 words
An amplifier circuit comprising: a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a fifth field effect transistor, a sixth field effect transistor, a seventh field effect transistor and an eighth field effect transistor; the first field effect transistor, the third field effect transistor and the fifth field effect transistor being NON (normally on) transistors; the second field effect transistor, the fourth field effect transistor, the sixth field effect transistor, the seventh field effect transistor and the eighth field effect transistor being NOF (normally off) transistors; drain terminals of the first field effect transistor, of the third field effect transistor, of the fifth field effect transistor and of the seventh field effect transistor connected to one another; source terminals of the second field effect transistor, of the fourth field effect transistor, of the sixth field effect transistor and of the eighth field effect transistor connected to one another; a source terminal of the first field effect transistor connected to a gate terminal of the first field effect transistor, to a drain terminal of the second field effect transistor, to a gate terminal of the fourth field effect transistor, to a gate terminal of the sixth field effect transistor and to a gate terminal of the eighth field effect transistor; a source terminal of the third field effect transistor connected to a gate terminal of the third field effect transistor, to a drain terminal of the fourth field effect transistor and to a gate terminal of the fifth field effect transistor; a source terminal of the fifth field effect transistor connected to a drain terminal of the sixth field effect transistor and to a gate terminal of the seventh field effect transistor; a source terminal of the seventh field effect transistor connected to a drain terminal of the eighth field effect transistor and being an output of the amplifier circuit; means for limiting the output of the amplifier circuit.
Claim 10
Dependent Claim
329 words
An amplifier circuit comprising: a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a fifth field effect transistor, a sixth field effect transistor, a seventh field effect transistor and an eighth field effect transistor; the first field effect transistor, the third field effect transistor and the fifth field effect transistor being NON (normally on) transistors; the second field effect transistor, the fourth field effect transistor, the sixth field effect transistor, the seventh field effect transistor and the eighth field effect transistor being NOF (normally off) transistors; drain terminals of the first field effect transistor, of the third field effect transistor, of the fifth field effect transistor and of the seventh field effect transistor connected to one another; source terminals of the second field effect transistor, of the fourth field effect transistor, of the sixth field effect transistor and of the eighth field effect transistor connected to one another; a source terminal of the first field effect transistor connected to a gate terminal of the first field effect transistor, to a drain terminal of the second field effect transistor, to a gate terminal of the fourth field effect transistor, to a gate terminal of the sixth field effect transistor and to a gate terminal of the eighth field effect transistor; a source terminal of the third field effect transistor connected to a gate terminal of the third field effect transistor, to a drain terminal of the fourth field effect transistor and to a gate terminal of the fifth field effect transistor; a source terminal of the fifth field effect transistor connected to a drain terminal of the sixth field effect transistor and to a gate terminal of the seventh field effect transistor; a source terminal of the seventh field effect transistor connected to a drain terminal of the eighth field effect transistor and being an output of the amplifier circuit; means for limiting the output of the amplifier circuit.
Claim 11
Dependent Claim
46 words
The amplifier circuit according to claim 6, wherein said means for limiting is a clamp diode having a positive terminal connected to the drain terminal of the eighth field effect transistor and a negative terminal connected to the source terminal of the eighth field effect transistor.
Claim 12
Dependent Claim
152 words
The amplifier circuit according to claim 6, wherein the means for limiting has: a ninth field effect transistor; a gate terminal of the ninth field effect transistor connected to the drain terminal of the sixth field effect transistor; a drain terminal of the ninth field effect transistor connected to the gate terminal of the seventh field effect transistor; a first diode having a positive terminal and a negative terminal and a second diode having a positive terminal and a negative terminal; a source terminal of the ninth field effect transistor connected to the positive terminal of the first diode; the source terminal of the third field effect transistor connected to the positive terminal of the second diode; the negative terminals of the first diode and of the second diode connected to one another; and the negative terminal of the first diode connected to the source terminal of the eighth field effect transistor.
Claim 13
Dependent Claim
169 words
The amplifier circuit according to claim 6, wherein the means for limiting has: a third diode having a positive terminal and a negative terminal; a tenth field effect transistor and an eleventh field effect transistor; the positive terminal of the third diode connected to the negative terminal of the second diode; the negative terminal of the third diode connected to the source terminal of the eighth field effect transistor; a drain terminal of the tenth field effect transistor connected to the drain terminal of the seventh field effect transistor; a source terminal of the tenth field effect transistor connected to a gate terminal of the tenth field effect transistor, to a drain terminal of the eleventh field effect transistor and to the positive terminal of the third diode; a source terminal of the eleventh field effect transistor connected to the source terminal of the eighth field effect transistor; and a gate terminal of the eleventh field effect transistor connected to the drain terminal of the eighth field effect transistor.
References Cited (Backward Citations)
DE2649356A1
Cited
EP0055795A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-10-22 | 1994-04-23 | 1994-10-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-10-22 | 1998-04-23 | 1998-10-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-10-22 | 2002-04-23 | 2002-10-23 | $7700.00 | Window Closed / Lapsed |