CMOS output driver which can tolerate an output voltage greater than the supply voltage without latchup or increased leakage current

Claim 2

A mixed mode buffer circuit including a first input, a second input, and an output, comprising: a first transistor of a first conductivity type having a first electrode, a control electrode coupled for receiving a first supply voltage, and a second electrode coupled to the first input; a first output transistor of a second conductivity type having a first electrode coupled to the output, a control electrode coupled to said first electrode of said first transistor, a second electrode coupled for receiving said first supply voltage, and a bulk electrode; a second output transistor of said first conductivity type having a first electrode coupled to the output, a control electrode coupled to the second input, and a second electrode coupled for receiving a second supply voltage; and a second transistor of said first conductivity type having a first electrode and a control electrode coupled for receiving said first supply voltage, and a second electrode coupled to said bulk electrode of said first output transistor wherein said second transistor biases said bulk electrode of said first output transistor to a different voltage potential than said second electrode of said first output transistor.

Claim 3

The mixed mode buffer circuit as recited in claim 1 further including a third transistor of said second conductivity type having a first electrode and bulk electrode coupled to said bulk electrode of said first output transistor, a control electrode coupled to the output, and a second electrode coupled for receiving said first supply voltage.

Claim 4

The mixed mode buffer circuit as recited in claim 2 further including a fourth transistor of said second conductivity type having a first electrode coupled to said control electrode of said first output transistor, a control electrode coupled for receiving said first supply voltage, a second electrode coupled to the output, and a bulk electrode coupled to said bulk electrode of said first output transistor.

Claim 5

The mixed mode buffer circuit as recited in claim 3 further including a fifth transistor of said second conductivity type having a first electrode and a bulk electrode coupled to said bulk electrode of said first output transistor, a control electrode coupled to said control electrode of said first output transistor, and a second electrode coupled for receiving said first supply voltage.

Claim 6

The mixed mode buffer circuit as recited in claim 4 further including a sixth transistor of said second conductivity type having a first electrode and a bulk electrode coupled to said bulk electrode of said first output transistor, a control electrode coupled for receiving said first supply voltage, and a second electrode coupled to the output.

Claim 7

The mixed mode buffer circuit as recited in claim 5 further including a seventh transistor of said second conductivity type having a first electrode coupled to said control electrode of said first output transistor, a control electrode coupled to the output, a second electrode coupled to the first input, and a bulk electrode coupled to said bulk electrode of said first output transistor.

Claim 8

The mixed mode buffer circuit as recited in claim 6 wherein a threshold voltage magnitude of said first output transistor is greater than a threshold voltage magnitude of said first transistor.

Claim 9

The mixed mode buffer circuit as recited in claim 7 wherein a threshold voltage magnitude of said first output transistor is greater than threshold voltage magnitude of said second transistor.

Claim 10

The mixed mode buffer circuit as recited in claim 8 wherein a threshold voltage magnitude of said sixth transistor is less than said threshold voltage magnitude of said first output transistor minus said threshold voltage magnitude of said second transistor.

Claim 11

A mixed mode buffer circuit including a first input, a second input, and an output, comprising: a first transistor of a first conductivity type having a first electrode, a control electrode coupled for receiving a first supply voltage, and a second electrode coupled to the first input; a first output transistor of a second conductivity type having a first electrode coupled to the output, a control electrode coupled to said first electrode of said first transistor, a second electrode coupled for receiving said first supply voltage, and a bulk electrode; a second output transistor of said first conductivity type having a first electrode coupled to the output, a control electrode coupled to the second input and a second electrode coupled for receiving a second supply voltage; a second transistor of said second conductivity type having a first electrode and bulk electrode coupled to said bulk electrode of said first output transistor, a control electrode coupled to the output, and a second electrode coupled for receiving said first supply voltage, said second transistor being enabled for providing a bias voltage to said bulk of said first output transistor when a voltage at the output of the mixed mode buffer circuit is within a first voltage range, said first voltage range ranging from said second supply voltage to a first predetermined voltage; and a first bulk bias circuit having a terminal coupled to said bulk electrode of said first output transistor, said first bulk bias circuit being enabled for providing a bias voltage to said bulk electrode of said first output transistor when said voltage at the output of mixed mode buffer circuit is within a second voltage range, said second voltage ranging from said first predetermined voltage to a second predetermined voltage; a third transistor of said second conductivity type having a first electrode coupled to said control electrode of said first output transistor, a control electrode coupled for receiving said first supply voltage, a second electrode coupled to the output, and a bulk electrode coupled to said bulk electrode of said first output transistor; and a second bulk bias circuit having a terminal coupled to said bulk electrode of said first output transistor, said second bulk bias circuit applying a bias voltage to said bulk electrode of said first output transistor when a logic zero is applied to the first input of the mixed mode buffer circuit.

Claim 12

A mixed mode buffer circuit including a first input, a second input, and an output, comprising: a first transistor of a first conductivity type having a first electrode, a control electrode coupled for receiving a first supply voltage, and a second electrode coupled to the first input; a first output transistor of a second conductivity type having a first electrode coupled to the output, a control electrode coupled to said first electrode of said first transistor, a second electrode coupled for receiving said first supply voltage, and a bulk electrode; a second output transistor of said first conductivity type having a first electrode coupled to the output, a control electrode coupled to the second input and a second electrode coupled for receiving a second supply voltage; a second transistor of said second conductivity type having a first electrode and bulk electrode coupled to said bulk electrode of said first output transistor, a control electrode coupled to the output, and a second electrode coupled for receiving said first supply voltage, said second transistor being enabled for providing a bias voltage to said bulk of said first output transistor when a voltage at the output of the mixed mode buffer circuit is within a first voltage range, said first voltage range ranging from said second supply voltage to a first predetermined voltage; and a first bulk bias circuit having a terminal coupled to said bulk electrode of said first output transistor, said first bulk bias circuit being enabled for providing a bias voltage to said bulk electrode of said first output transistor when said voltage at the output of mixed mode buffer circuit is within a second voltage range, said second voltage ranging from said first predetermined voltage to a second predetermined voltage; a third transistor of said second conductivity type having a first electrode coupled to said control electrode of said first output transistor, a control electrode coupled for receiving said first supply voltage, a second electrode coupled to the output, and a bulk electrode coupled to said bulk electrode of said first output transistor; and a second bulk bias circuit having a terminal coupled to said bulk electrode of said first output transistor, said second bulk bias circuit applying a bias voltage to said bulk electrode of said first output transistor when a logic zero is applied to the first input of the mixed mode buffer circuit.

Claim 13

A mixed mode buffer circuit as recited in claim 10 wherein said first bulk bias circuit comprises a transistor of said first conductivity type having a first electrode and control electrode coupled for receiving said first supply voltage, and a second electrode coupled to said terminal of said first bulk bias circuit.

Claim 14

A mixed mode buffer circuit as recited in claim 11 wherein a threshold voltage magnitude of said first output transistor is greater than a threshold voltage magnitude of said transistor of said first bulk bias circuit.

Claim 15

A mixed mode buffer circuit as recited in claim 12 further including a third bulk bias circuit having a terminal coupled to said bulk electrode of said first output transistor, said third bulk bias circuit being enabled for providing a bias voltage to said bulk electrode of said first output transistor when said voltage at the output of the mixed mode buffer exceeds said second predetermined voltage.

Claim 16

A mixed mode buffer circuit as recited in claim 13 wherein said third bulk bias circuit comprises a transistor of said second conductivity type having a first electrode and bulk electrode coupled to said bulk electrode of said first output transistor, a control electrode coupled for receiving said first supply voltage, and a second electrode coupled to the output.

Claim 17

A mixed mode buffer circuit as recited in claim 14 wherein a threshold voltage magnitude of said transistor of said third bulk bias circuit is less than said threshold voltage magnitude of said first output transistor minus said threshold voltage magnitude of said transistor of said first bulk bias circuit.

Claim 18

A mixed mode buffer circuit as recited in claim 10 wherein a threshold voltage magnitude of said first output transistor is greater than a threshold voltage magnitude of said first transistor.

Claim 19

A mixed mode buffer circuit as recited in claim 18 further including a fourth transistor of said second conductivity type having a first electrode coupled to said control electrode of said first output transistor, a control electrode coupled to the output, a second electrode coupled to the first input, and a bulk electrode coupled to said bulk electrode of said first output transistor.

Claim 20

A buffer circuit having a first input, a second input, and an output, the buffer circuit comprising: a first output transistor of a first conductivity type having a first electrode coupled to the output, a control electrode, a second electrode coupled for receiving a first supply voltage, and a bulk electrode; a second output transistor of a second conductivity type having a first electrode coupled to the output, a control electrode coupled to the second input, and a second electrode coupled for receiving a second supply voltage; a pass transistor of said second conductivity type having a first electrode coupled to said control electrode of said first output transistor, a control electrode coupled for receiving said first supply voltage, and a second electrode coupled to the first input; a first transistor of said second conductivity type having a first electrode and gate electrode coupled for receiving said first supply voltage, and a second electrode coupled to said bulk electrode of said first output transistor; a second transistor of said first conductivity type having a first electrode and bulk electrode coupled to said bulk electrode of said first output transistor, a control electrode coupled for receiving said first supply voltage, and a second electrode coupled to the output; a third transistor of said first conductivity type having a first electrode coupled to said control electrode of said first output transistor, a control electrode coupled for receiving a first supply voltage, a second electrode coupled to the output, and a bulk electrode coupled to said bulk electrode of said first output transistor; a fourth transistor of said first conductivity type having a first electrode and bulk electrode coupled to said bulk electrode of said first output transistor, a control electrode coupled to the output, and a second electrode coupled for receiving said first supply voltage; and a fifth transistor of said first conductivity type having a first electrode and a bulk electrode coupled to said bulk electrode of said first output transistor, a control electrode coupled to said control electrode of said first output transistor, and a second electrode coupled for receiving said first supply voltage.

Claim 21

A buffer circuit having a first input, a second input, and an output, the buffer circuit comprising: a first output transistor of a first conductivity type having a first electrode coupled to the output, a control electrode, a second electrode coupled for receiving a first supply voltage, and a bulk electrode; a second output transistor of a second conductivity type having a first electrode coupled to the output, a control electrode coupled to the second input, and a second electrode coupled for receiving a second supply voltage; a pass transistor of said second conductivity type having a first electrode coupled to said control electrode of said first output transistor, a control electrode coupled for receiving said first supply voltage, and a second electrode coupled to the first input; a first transistor of said second conductivity type having a first electrode and gate electrode coupled for receiving said first supply voltage, and a second electrode coupled to said bulk electrode of said first output transistor; a second transistor of said first conductivity type having a first electrode and bulk electrode coupled to said bulk electrode of said first output transistor, a control electrode coupled for receiving said first supply voltage, and a second electrode coupled to the output; a third transistor of said first conductivity type having a first electrode coupled to said control electrode of said first output transistor, a control electrode coupled for receiving a first supply voltage, a second electrode coupled to the output, and a bulk electrode coupled to said bulk electrode of said first output transistor; a fourth transistor of said first conductivity type having a first electrode and bulk electrode coupled to said bulk electrode of said first output transistor, a control electrode coupled to the output, and a second electrode coupled for receiving said first supply voltage; and a fifth transistor of said first conductivity type having a first electrode and a bulk electrode coupled to said bulk electrode of said first output transistor, a control electrode coupled to said control electrode of said first output transistor, and a second electrode coupled for receiving said first supply voltage.

Claim 22

A buffer circuit as recited in claim 18 wherein a threshold voltage magnitude of said first transistor is less than a threshold voltage magnitude of said first output transistor.

Claim 23

A buffer circuit as recited in claim 19 wherein a threshold voltage magnitude of said second transistor is less than a said threshold voltage magnitude of said first output transistor minus said threshold voltage magnitude of said first transistor.

Claim 24

The buffer circuit of claim 17 further including a sixth transistor of said second conductivity type having a first electrode coupled to said control electrode of said first output transistor, a control electrode coupled to the output, a second electrode coupled to the first input, and a bulk electrode coupled to said bulk electrode of said first output transistor.