Boundary scan cell circuit and boundary scan test circuit

Claim 2

A boundary scan cell circuit comprising: a logic signal input terminal at which an external logic signal enters said boundary scan cell circuit; a scan signal input terminal at which an external scan signal enters said boundary scan cell circuit; a scan signal output terminal at which a scan signal leaves said boundary scan cell circuit; an input logic signal storage which latches a logic signal from said logic signal input terminal for a predetermined length of time and outputs it; an XOR generator which generates the XOR of a logic signal from said input logic signal storage with a delay of a predetermined length of time and a current logic signal from said logic signal input terminal; and a scan selector which selects one of a scan signal from said scan signal input terminal and an XOR signal from said XOR generator according to the logic state of a control signal and outputs a signal thus selected to outside said boundary scan cell circuit through said scan signal output terminal.

Claim 3

The boundary scan cell circuit as in claim 1, further comprising: an input signal selector which selects one of a logic signal received from said logic signal input terminal and a scan signal received from said scan signal input terminal according to the logic state of a control signal and outputs a signal thus selected to said XOR generator; wherein: said scan selector's input is connected to said input signal selector's output as well as to said XOR generator's output; said input logic signal storage, formed by a flip-flop for holding an input logic signal whose input is connected to said scan selector's output and whose output is connected to said scan signal output terminal, outputs either one of an input logic signal and an XOR signal according to the logic state of a clock signal; and said scan signal output terminal is connected to a non-inverting output terminal of said flip-flop.

Claim 4

A boundary scan cell circuit comprising: a logic signal output terminal at which a logic signal is output, a scan signal input terminal at which an external scan signal enters said boundary scan cell circuit; a scan signal output terminal at which a scan signal leaves said boundary scan cell circuit; an input scan signal storage which latches a scan signal received from said scan signal input terminal for a predetermined length of time and outputs it; an inversion signal generator which accepts the output of said input scan signal storage and inverts it to give an inverted scan signal; an input signal selector whose input is connected to said scan signal input terminal as well as to said inversion signal generator and whose output is connected to said input scan signal storage, said input signal selector alternately selecting input scan signals from said scan signal input terminal and inverted scan signals from said inversion signal generator according to the logic state of a control signal and outputting a signal thus selected; and an alternate signal output unit which latches a signal selected by said input signal selector for a predetermined length of time and outputs it to outside said boundary scan cell circuit through said logic signal output terminal; wherein said scan signal output terminal is connected to a signal line between said scan signal input terminal and said input signal selector.

Claim 5

A boundary scan cell circuit comprising: a logic signal output terminal at which a logic signal is output, a scan signal input terminal at which an external scan signal enters said boundary scan cell circuit; a scan signal output terminal at which a scan signal leaves said boundary scan cell circuit; an input scan signal storage which latches a scan signal received from said scan signal input terminal for a predetermined length of time and outputs it; an inversion signal generator which accepts the output of said input scan signal storage and inverts it to give an inverted scan signal; an input signal selector whose input is connected to said scan signal input terminal as well as to said inversion signal generator and whose output is connected to said input scan signal storage, said input signal selector alternately selecting input scan signals from said scan signal input terminal and inverted scan signals from said inversion signal generator according to the logic state of a control signal and outputting a signal thus selected; and an alternate signal output unit which latches a signal selected by said input signal selector for a predetermined length of time and outputs it to outside said boundary scan cell circuit through said logic signal output terminal; wherein said scan signal output terminal is connected to a signal line between said scan signal input terminal and said input signal selector.

Claim 6

The boundary scan cell circuit as in claim 3, wherein: said input scan signal storage, inversion signal generator, and alternate signal output unit are formed by a flip-flop for holding an input scan signal having a non-inverting output terminal and an inverting output terminal, said flip-flop being capable of outputting the non-inverted signal of an input signal through said non-inverting output terminal or the inverted signal of an input signal through said inverting output terminal according to the logic state of a clock signal; said logic signal output terminal is connected to said non-inverting output terminal of said flip-flop; and said input signal selector is a selector whose input is connected to said scan signal input terminal as well as to said inverting output terminal of said flip-flop and whose output is connected to an input terminal of said flip-flop.

Claim 7

The boundary scan cell circuit as in either claim 1 or claim 2 further including: a logical signal output terminal at which a logical signal is output, an input scan signal storage which latches a scan signal received from said scan signal input terminal for a predetermined length of time and outputs it; an inversion signal generator which accepts the output of said input scan signal storage and inverts it to give an inverted scan signal; and an output logic signal selector which accepts the output of said input scan signal storage and the output of said inversion signal generator, selects one of the scan signal and the inverted scan signal according to the logic state of a control signal, and outputs a signal thus selected to outside said boundary scan cell circuit through said logic signal output terminal.

Claim 8

In a boundary scan test circuit comprising (a) a plurality of integrated circuits each of which has an internal logic, an input pin at which an external logic signal enters said internal logic, and an output pin at which a logic signal leaves said internal logic; (b) a wire mount, disposed between the input pin of any one of said plurality of integrated circuits and the output pin of the other integrated circuit, onto which a wire, subjected to interconnection testing, is mounted; (c) input boundary scan cell circuits each disposed between the input pin of each of said plurality of integrated circuits and said internal logic of each of said plurality of integrated circuits; (d) output boundary scan cell circuits each disposed between the output pin of each of said plurality of integrated circuits and said internal logic of each of said plurality of integrated circuits; and (e) a scan path for connecting said boundary scan cell circuits in series, each of said input boundary scan cell circuits comprising: a logic signal input terminal in connection with said input pin; a scan signal input terminal for receiving a scan signal from said scan path; a scan signal output terminal for providing a scan signal to said scan path; an input logic signal storage which latches a logic signal from said logic signal input terminal for a predetermined length of time and outputs it; an XOR generator which generates the XOR of a logic signal from said input logic signal storage with a delay of a predetermined length of time and a current logic signal from said logic signal input terminal; and a scan selector which selects one of a scan signal from said scan signal input terminal and an XOR signal from said XOR generator according to the logic state of a control signal and outputs a signal thus selected onto said scan path through said scan signal output terminal.

Claim 9

In a boundary scan test circuit comprising (a) a plurality of integrated circuits each of which has an internal logic, an input pin at which an external logic signal enters said internal logic, and an output pin at which a logic signal leaves said internal logic; (b) a wire mount, disposed between the input pin of any one of said plurality of integrated circuits and the output pin of the other integrated circuit, onto which a wire, subjected to interconnection testing, is mounted; (c) input boundary scan cell circuits each disposed between the input pin of each of said plurality of integrated circuits and said internal logic of each of said plurality of integrated circuits; (d) output boundary scan cell circuits each disposed between the output pin of each of said plurality of integrated circuits and said internal logic of each of said plurality of integrated circuits; and (e) a scan path for connecting said boundary scan cell circuits in series, each of said input boundary scan cell circuits comprising: a logic signal input terminal in connection with said input pin; a scan signal input terminal for receiving a scan signal from said scan path; a scan signal output terminal for providing a scan signal to said scan path; an input logic signal storage which latches a logic signal from said logic signal input terminal for a predetermined length of time and outputs it; an XOR generator which generates the XOR of a logic signal from said input logic signal storage with a delay of a predetermined length of time and a current logic signal from said logic signal input terminal; and a scan selector which selects one of a scan signal from said scan signal input terminal and an XOR signal from said XOR generator according to the logic state of a control signal and outputs a signal thus selected onto said scan path through said scan signal output terminal.

Claim 10

The boundary scan test circuit as in claim 6 further including: an input signal selector which selects one of a logic signal received from said logic signal input terminal and a scan signal received from said scan signal input terminal according to the logic state of a control signal and outputs a signal thus selected to said XOR generator; wherein: said scan selector's input is connected to said input signal selector's output as well as to said XOR generator's output; said input logic signal storage, formed by a flip-flop for holding an input logic signal whose input is connected to said scan selector's output and whose output is connected to said scan signal output terminal, outputs either one of an input logic signal and an XOR signal according to the logic state of a clock signal; and said scan signal output terminal is connected to a non-inverting output terminal of said flip-flop.

Claim 11

In a boundary scan test circuit comprising (a) a plurality of integrated circuits each of which has an internal logic, an input pin at which an external logic signal enters said internal logic, and an output pin at which a logic signal leaves said internal logic; (b) a wire mount, disposed between the input pin of any one of said plurality of integrated circuits and the output pin of the other integrated circuit, onto which a wire, subjected to interconnection testing, is mounted; (c) input boundary scan cell circuits each disposed between the input pin of each of said plurality of integrated circuits and said internal logic of each of said plurality of integrated circuits; (d) output boundary scan cell circuits each disposed between the output pin of each of said plurality of integrated circuits and said internal logic of each of said plurality of integrated circuits; and (e) a scan path for connecting said boundary scan cell circuits in series, each of said output boundary scan cell circuits comprising: a logic signal output terminal in connection with said output pin; a scan signal output terminal for providing a scan signal onto said scan path; a scan signal input terminal for receiving a scan signal from said scan path; an input scan signal storage which latches a scan signal from said scan signal input terminal for a predetermined length of time and outputs it; an inversion signal generator which accepts the output of said input scan signal storage and inverts it to give an inverted scan signal; an input signal selector whose input is connected to said scan signal input terminal as well as to said inversion signal generator and whose output is connected to said input scan signal storage, said input signal selector alternately selecting input scan signals from said scan signal input terminal and inverted scan signals from said inversion signal generator according to the logic state of a control signal and outputting a signal thus selected; and an alternate signal output unit which latches a signal selected by said input signal selector for a predetermined length of time and outputs it; wherein said scan signal output terminal is connected to a signal line between said scan signal input terminal and said input signal selector.

Claim 12

In a boundary scan test circuit comprising (a) a plurality of integrated circuits each of which has an internal logic, an input pin at which an external logic signal enters said internal logic, and an output pin at which a logic signal leaves said internal logic; (b) a wire mount, disposed between the input pin of any one of said plurality of integrated circuits and the output pin of the other integrated circuit, onto which a wire, subjected to interconnection testing, is mounted; (c) input boundary scan cell circuits each disposed between the input pin of each of said plurality of integrated circuits and said internal logic of each of said plurality of integrated circuits; (d) output boundary scan cell circuits each disposed between the output pin of each of said plurality of integrated circuits and said internal logic of each of said plurality of integrated circuits; and (e) a scan path for connecting said boundary scan cell circuits in series, each of said output boundary scan cell circuits comprising: a logic signal output terminal in connection with said output pin; a scan signal output terminal for providing a scan signal onto said scan path; a scan signal input terminal for receiving a scan signal from said scan path; an input scan signal storage which latches a scan signal from said scan signal input terminal for a predetermined length of time and outputs it; an inversion signal generator which accepts the output of said input scan signal storage and inverts it to give an inverted scan signal; an input signal selector whose input is connected to said scan signal input terminal as well as to said inversion signal generator and whose output is connected to said input scan signal storage, said input signal selector alternately selecting input scan signals from said scan signal input terminal and inverted scan signals from said inversion signal generator according to the logic state of a control signal and outputting a signal thus selected; and an alternate signal output unit which latches a signal selected by said input signal selector for a predetermined length of time and outputs it; wherein said scan signal output terminal is connected to a signal line between said scan signal input terminal and said input signal selector.

Claim 13

The boundary scan test circuit as in claim 8, wherein: said input scan signal storage, inversion signal generator, and alternate signal output unit are formed by a flip-flop for holding an input scan signal having a non-inverting output terminal and an inverting output terminal, said flip-flop being capable of outputting the non-inverted signal of an input signal through said non-inverting output terminal and the inverted signal of an input signal through said inverting output terminal; said logic signal output terminal is connected to said non-inverting output terminal of said flip-flop; and said input signal selector is a selector whose input is connected to said scan signal input terminal as well as to said inverting output terminal of said flip-flop and whose output is connected to an input terminal of said flip-flop.

Claim 14

The boundary scan test circuit as in either claim 6 or claim 7, wherein: an integrated circuit having therein said input boundary scan cell circuits has output boundary scan cell circuits, said each output boundary scan cell circuit comprising: a logic signal output terminal in connection with said output pin; a scan signal input terminal for receiving a scan signal from said scan path; a scan signal output terminal for providing a scan signal to said scan path; an input scan signal storage which latches a scan signal received from said scan signal input terminal for a predetermined length of time and outputs it; an inversion signal generator which accepts the output of said input scan signal storage and inverts it to give an inverted scan signal; an input signal selector whose input is connected to said scan signal input terminal as well as to said inversion signal generator and whose output is connected to said input scan signal storage, said input signal selector alternately selecting input scan signals from said scan signal input terminal and inverted scan signals from said inversion signal generator according to the logic state of a control signal and outputting a signal thus selected; and an alternate signal output unit which latches a signal selected by said input signal selector for a predetermined length of time and outputs it; wherein said scan signal output terminal is connected to a signal line between said scan signal input terminal and said input signal selector.

Claim 15

The boundary scan test circuit as in either claim 8 or claim 9, wherein: an integrated circuit having therein said output boundary scan cell circuits has input boundary scan cell circuits, said each input boundary scan cell circuit comprising: a logic signal input terminal in connection with said input pin; a scan signal input terminal for receiving a scan signal from said scan path; a scan signal output terminal for providing a scan signal to said scan path; an input logic signal storage which latches a logic signal from said logic signal input terminal for a predetermined length of time and outputs it; an XOR generator which generates the XOR of a logic signal from said input logic signal storage with a delay of a predetermined length of time and a current logic signal from said logic signal input terminal; and a scan selector which selects one of a scan signal from said scan signal input terminal and an XOR signal from said XOR generator according to the logic state of a control signal and outputs a signal thus selected onto said scan path through said scan signal output terminal.

Claim 16

In a boundary scan test circuit comprising (a) a plurality of integrated circuits each of which has an internal logic, an input pin at which an external logic signal enters said internal logic, and an output pin at which a logic signal leaves said internal logic; (b) a wire mount, disposed between the input pin of any one of said plurality of integrated circuits and the output pin of the other integrated circuit, onto which a wire, subjected to interconnection testing, is mounted; (c) input boundary scan cell circuits each disposed between the input pin of each of said plurality of integrated circuits and said internal logic of each of said plurality of integrated circuits; (d) output boundary scan cell circuits each disposed between the output pin of each of said plurality of integrated circuits and said internal logic of each of said plurality of integrated circuits; and (e) a scan path for connecting said boundary scan cell circuits in series, each of said input boundary scan cell circuit and said output boundary scan cell circuit comprising: a logic signal input terminal having a structure capable of receiving a logic signal; a scan signal input terminal for receiving a scan signal from said scan path; a scan signal output terminal for providing a scan signal to said scan path; an input logic signal storage which latches a logic signal from said logic signal input terminal for a predetermined length of time and outputs it; an XOR generator which generates the XOR of a logic signal from said input logic signal storage with a delay of a predetermined length of time and a current logic signal from said logic signal input terminal; a scan selector which selects one of a scan signal from said scan signal input terminal and an XOR signal from said XOR generator according to the logic state of a control signal and outputs a signal thus selected to said scan signal output terminal; a logic signal output terminal at which a logic signal is output; an input scan signal storage which latches a scan signal received from said scan signal input terminal for a predetermined length of time and outputs it; an inversion signal generator which accepts the output of said input scan signal storage and inverts it to give an inverted scan signal; an input signal selector whose input is connected to said scan signal input terminal as well as to said inversion signal generator and whose output is connected to said input scan signal storage, said input signal selector alternately selecting input scan signals from said scan signal input terminal and inverted scan signals from said inversion signal generator according to the logic state of a control signal and outputting a signal thus selected; and an alternate signal output unit which latches a signal selected by said input signal selector for a predetermined length of time and outputs it.

Claim 17

In a boundary scan test circuit comprising (a) a plurality of integrated circuits each of which has an internal logic, an input pin at which an external logic signal enters said internal logic, and an output pin at which a logic signal leaves said internal logic; (b) a wire mount, disposed between the input pin of any one of said plurality of integrated circuits and the output pin of the other integrated circuit, onto which a wire, subjected to interconnection testing, is mounted; (c) input boundary scan cell circuits each disposed between the input pin of each of said plurality of integrated circuits and said internal logic of each of said plurality of integrated circuits; (d) output boundary scan cell circuits each disposed between the output pin of each of said plurality of integrated circuits and said internal logic of each of said plurality of integrated circuits; and (e) a scan path for connecting said boundary scan cell circuits in series, each of said input boundary scan cell circuit and said output boundary scan cell circuit comprising: a logic signal input terminal having a structure capable of receiving a logic signal; a scan signal input terminal for receiving a scan signal from said scan path; a scan signal output terminal for providing a scan signal to said scan path; an input logic signal storage which latches a logic signal from said logic signal input terminal for a predetermined length of time and outputs it; an XOR generator which generates the XOR of a logic signal from said input logic signal storage with a delay of a predetermined length of time and a current logic signal from said logic signal input terminal; a scan selector which selects one of a scan signal from said scan signal input terminal and an XOR signal from said XOR generator according to the logic state of a control signal and outputs a signal thus selected to said scan signal output terminal; a logic signal output terminal at which a logic signal is output; an input scan signal storage which latches a scan signal received from said scan signal input terminal for a predetermined length of time and outputs it; an inversion signal generator which accepts the output of said input scan signal storage and inverts it to give an inverted scan signal; an input signal selector whose input is connected to said scan signal input terminal as well as to said inversion signal generator and whose output is connected to said input scan signal storage, said input signal selector alternately selecting input scan signals from said scan signal input terminal and inverted scan signals from said inversion signal generator according to the logic state of a control signal and outputting a signal thus selected; and an alternate signal output unit which latches a signal selected by said input signal selector for a predetermined length of time and outputs it.

Claim 18

A boundary scan test method by the use of a boundary scan test circuit comprising: (a) a plurality of integrated circuits each of which has an internal logic, an input pin at which an external logic signal enters said internal logic, and an output pin at which a logic signal leaves said internal logic; (b) input boundary scan cell circuits each disposed between the input pin of each of said plurality of integrated circuits and said internal logic of each of said plurality of integrated circuits; (c) output boundary scan cell circuits each disposed between the output pin of each of said plurality of integrated circuits and said internal logic of each of said plurality of integrated circuits; and (d) a scan path for connecting said boundary scan cell circuits in series, said method comprising the steps of: connecting a wire subjected to testing between the output pin of at least one of said plurality of integrated circuits and the input pin of another integrated circuit; making said output boundary scan cell circuit in connection with the output pin of said integrated circuit supply non-inverted logic signals and inverted logic signals one after the other at predetermined intervals; latching a logic signal, applied to said input boundary scan cell circuit connected to the input pin of said integrated circuit, for a predetermined length of time; generating the XOR of a current logic signal input at said input pin and a previous logic signal with a delay of a predetermined length of time; and selecting one of an incoming scan signal and an XOR signal for scan-out of a signal thus selected onto said scan path.

Claim 19

A boundary scan test method by the use of a boundary scan test circuit comprising: (a) a plurality of integrated circuits each of which has an internal logic, an input pin at which an external logic signal enters said internal logic, and an output pin at which a logic signal leaves said internal logic; (b) input boundary scan cell circuits each disposed between the input pin of each of said plurality of integrated circuits and said internal logic of each of said plurality of integrated circuits; (c) output boundary scan cell circuits each disposed between the output pin of each of said plurality of integrated circuits and said internal logic of each of said plurality of integrated circuits; and (d) a scan path for connecting said boundary scan cell circuits in series, said method comprising the steps of: connecting a wire subjected to testing between the output pin of at least one of said plurality of integrated circuits and the input pin of another integrated circuit; making said output boundary scan cell circuit in connection with the output pin of said integrated circuit supply non-inverted logic signals and inverted logic signals one after the other at predetermined intervals; latching a logic signal, applied to said input boundary scan cell circuit connected to the input pin of said integrated circuit, for a predetermined length of time; generating the XOR of a current logic signal input at said input pin and a previous logic signal with a delay of a predetermined length of time; and selecting one of an incoming scan signal and an XOR signal for scan-out of a signal thus selected onto said scan path.

Claim 20

A boundary scan test method by the use of a boundary scan test circuit comprising: (a) a plurality of integrated circuits each of which has an internal logic, an input pin at which an external logic signal enters said internal logic, and an output pin at which a logic signal leaves said internal logic; (b) input boundary scan cell circuits each disposed between the input pin of each of said plurality of integrated circuits and said internal logic of each of said plurality of integrated circuits; (c) output boundary scan cell circuits each disposed between the output pin of each of said plurality of integrated circuits and said internal logic of each of said plurality of integrated circuits; and (d) a scan path for connecting said boundary scan cell circuits in series, said method comprising the steps of: connecting a wire subjected to testing between the output pin of at least one of said plurality of integrated circuits and the input pin of another integrated circuit; performing scan-in of a scan signal applied to said output boundary scan cell circuit in connection with the output pin of said integrated circuit, and latching same for a predetermined length of time; inverting such a scan signal thus latched to give an inverted scan signal; and alternately selecting an current input scan signal to said output boundary scan cell circuit and a previous, inverted scan signal so as to apply a signal thus selected to said wire subjected to testing.

Claim 21

A boundary scan test method by the use of a boundary scan test circuit comprising: (a) a plurality of integrated circuits each of which has an internal logic, an input pin at which an external logic signal enters said internal logic, and an output pin at which a logic signal leaves said internal logic; (b) input boundary scan cell circuits each disposed between the input pin of each of said plurality of integrated circuits and said internal logic of each of said plurality of integrated circuits; (c) output boundary scan cell circuits each disposed between the output pin of each of said plurality of integrated circuits and said internal logic of each of said plurality of integrated circuits; and (d) a scan path for connecting said boundary scan cell circuits in series, said method comprising the steps of: connecting a wire subjected to testing between the output pin of at least one of said plurality of integrated circuits and the input pin of another integrated circuit; performing scan-in of a scan signal applied to said output boundary scan cell circuit in connection with the output pin of said integrated circuit, and latching same for a predetermined length of time; inverting such a scan signal thus latched to give an inverted scan signal; and alternately selecting an current input scan signal to said output boundary scan cell circuit and a previous, inverted scan signal so as to apply a signal thus selected to said wire subjected to testing.