US5319646A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Boundary-scan output cell with non-critical enable path
Assignee: NCR Voyix Corp
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Filing: 1991-09-18
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Granted: 1994-06-07
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Expires: 2011-09-18
Abstract
Abstract A boundary-scan output cell which includes critical data term and non-critical masking term paths without adding an extra layer of logic. The boundary-scan cell includes a multiplexer, a critical data path which transmits critical data terms, coupled to a first multiplexer input, a sampling circuit which transmits non-critical terms, term circuit coupled to a second multiplexer input, and a non-critical term path which transmits non-critical masking terms, coupled to the shift input of the multiplexer. Non-critical masking terms at the shift input are mimicked at the second input. Provision is also made for a test control circuit and a circuit for monitoring critical and non-critical terms.
Inventors
- 👤 David L. Simpson
- 👤 Wilson E. Smoak, III
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 09:04
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318541
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
236 words
A device for isolating an input/output pad from an integrated circuit comprising: a selector element having critical data term, non-critical masking term, and shift inputs, the device selecting the critical data term input during normal operation of the integrated circuit and the non-critical masking term input during both test and default operation of the integrated circuit, the selector element including a first multiplexer; a sampling circuit coupled to the non-critical masking term input of the first multiplexer including a second multiplexer having a term input and a previous device contents input, a shift register coupled to the output of the second multiplexer including a D-type flip-flop coupled to the output of the second multiplexer, and a latch coupled between the output of the shift register and the non-critical masking term input of the first multiplexer; a monitoring circuit, coupled between the system logic and the term input of the second multiplexer, the monitoring circuit including an inverter having a non-critical masking term input and a NAND gate having inverted non-critical mask term and critical data inputs; and a test control circuit including a first subcircuit coupled between the latch output and the non-critical mask input of the first multiplexer including an AND gate having latch and mode inputs, and a second subcircuit coupled between the system logic and the shift input of the first multiplexer including an OR gate having non-critical masking term and mode inputs.
Claim 2
Independent Claim
236 words
A device for isolating an input/output pad from an integrated circuit comprising: a selector element having critical data term, non-critical masking term, and shift inputs, the device selecting the critical data term input during normal operation of the integrated circuit and the non-critical masking term input during both test and default operation of the integrated circuit, the selector element including a first multiplexer; a sampling circuit coupled to the non-critical masking term input of the first multiplexer including a second multiplexer having a term input and a previous device contents input, a shift register coupled to the output of the second multiplexer including a D-type flip-flop coupled to the output of the second multiplexer, and a latch coupled between the output of the shift register and the non-critical masking term input of the first multiplexer; a monitoring circuit, coupled between the system logic and the term input of the second multiplexer, the monitoring circuit including an inverter having a non-critical masking term input and a NAND gate having inverted non-critical mask term and critical data inputs; and a test control circuit including a first subcircuit coupled between the latch output and the non-critical mask input of the first multiplexer including an AND gate having latch and mode inputs, and a second subcircuit coupled between the system logic and the shift input of the first multiplexer including an OR gate having non-critical masking term and mode inputs.
Claim 3
Dependent Claim
165 words
A boundary-scan cell for testing a system logic and its pin connections comprising: a monitoring circuit including an inverter having a non-critical masking term input, and a NAND gate having an inverted non-critical masking term input and a critical data input, which produces a term output; a test control circuit including an OR gate having a non-critical masking input and a mode input; a first multiplexer having critical data input, non-critical term input, and a shift input coupled to the output of the test control circuit; and a sampling circuit coupled between the monitoring circuit and the non-critical term input of the first multiplexer including a second multiplexer having a term input from the monitoring circuit, a shift input, and a previous cell contents input, the sampling circuit further including a shift register coupled to the output of the second multiplexer including a D-type flip-flop, and a latch coupled between the output of the shift register and the non-critical term input of the first multiplexer.
Claim 4
Dependent Claim
165 words
A boundary-scan cell for testing a system logic and its pin connections comprising: a monitoring circuit including an inverter having a non-critical masking term input, and a NAND gate having an inverted non-critical masking term input and a critical data input, which produces a term output; a test control circuit including an OR gate having a non-critical masking input and a mode input; a first multiplexer having critical data input, non-critical term input, and a shift input coupled to the output of the test control circuit; and a sampling circuit coupled between the monitoring circuit and the non-critical term input of the first multiplexer including a second multiplexer having a term input from the monitoring circuit, a shift input, and a previous cell contents input, the sampling circuit further including a shift register coupled to the output of the second multiplexer including a D-type flip-flop, and a latch coupled between the output of the shift register and the non-critical term input of the first multiplexer.
Claim 5
Dependent Claim
42 words
The boundary-scan output cell as recited in claim 1, wherein the test control circuit further comprises: a first subcircuit coupled between the latch output and the non-critical term input of the first multiplexer including an AND gate having latch and made inputs.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-06-06 | 1997-12-06 | 1998-06-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-06-06 | 2001-12-06 | 2002-06-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-06-06 | 2005-12-06 | 2006-06-07 | $7700.00 | Window Closed / Lapsed |