Apparatus and method using analog viterbi decoding techniques

Claim 2

An analog Viterbi decoder comprising: branch metric calculation means for successively calculating branch metrics from received symbols to output the branch metrics; adder, comparator and selector (ACS) means for successively calculating pairs of path metrics by adding preselected pairs of branch metrics and preselected pairs of last path metrics, respectively, for comparing the pairs of calculated path metrics with each other to select paths having smaller path metric values, and for outputting path selection signals to be used in said selections; and path memory means for successively storing candidates for a decoded signal according to said path selection signals and for successively refining the candidates according to said path selection signals to obtain the decoded signal, said branch metric calculation means outputting said branch metrics in analog signal form, said ACS means performing said adding, comparing, and outputting in analog signal processes, said branch metric calculation means including a current conversion circuit for converting values of said received symbols to current signals, and a first addition circuit coupled to the current conversion circuit, for calculating current branch metrics from said current signals, said received symbols are input to the analog Viterbi decoder in digital signal form including a plurality of bits, and said current conversion circuit comprises a plurality of digital/analog conversion circuits for converting said received symbols into current signals.

Claim 3

An analog Viterbi decoder as claimed in claim 1, wherein said digital/analog conversion circuits include 2 n (n=0, 1, 2 . . . ) parallel connected constant current sources and an output current of each of said 2 n parallel connected constant current sources is controlled according to said digital signal form of the received symbols, whereby non-inverted and inverted current signals are output.

Claim 4

An analog Viterbi decoder as claimed in claim 2, wherein said 2 n parallel connected constant current sources are controlled by external control signals.

Claim 5

An analog Viterbi decoder comprising: branch metric calculation means for successively calculating branch metrics from received symbols to output the branch metrics; adder, comparator and selector (ACS) means for successively calculating pairs of path metrics by adding preselected pairs of branch metrics and preselected pairs of last path metrics, respectively, for comparing the pairs of calculated path metrics with each other to select paths having smaller path metric values, and for outputting path selection signals to be used in said selections; and path memory means for successively storing candidates for a decoded signal according to said path selection signals and for successively refining the candidates according to said path selection signals to obtain the decoded signal, said branch metric calculation means outputting said branch metrics in analog signal form, said ACS means performing said adding, comparing, and outputting in analog signal processes, said branch metric calculation means including a current conversion circuit for convening values of said received symbols to current signals, and a first addition circuit coupled to the current conversion circuit, for calculating current branch metrics from said current signals, said first addition circuit including a plurality of addition circuit blocks each including a number of first common base type transistor circuits connected in parallel with each other, the first common base type transistor circuits generating respective current branch metrics which are equal to each other.

Claim 6

An analog Viterbi decoder comprising: branch metric calculation means for successively calculating branch metrics from received symbols to output the branch metrics; adder, comparator and selector (ACS) means for successively calculating pairs of path metrics by adding preselected pairs of branch metrics and preselected pairs of last path metrics, respectively, for comparing the pairs of calculated path metrics with each other to select paths having smaller path metric values, and for outputting path selection signals to be used in said selections; and path memory means for successively storing candidates for a decoded signal according to said path selection signals and for successively refining the candidates according to said path selection signals to obtain the decoded signal, said branch metric calculation means outputting said branch metrics in analog signal form, said ACS means performing said adding, comparing, and outputting in analog signal processes, said branch metric calculation means including a current conversion circuit for convening values of said received symbols to current signals, and a first addition circuit coupled to the current conversion circuit, for calculating current branch metrics from said current signals, said first addition circuit including a plurality of addition circuit blocks each including a number of first common base type transistor circuits connected in parallel with each other, the first common base type transistor circuits generating respective current branch metrics which are equal to each other.

Claim 7

An analog Viterbi decoder as claimed in claim 4, wherein said ACS means includes a path metric memory for storing said path metrics in voltage signal form and for outputting current path metrics, a second addition circuit coupled to said path metric memory, for adding preselected pairs of said current branch metrics and preselected pairs of said current path metrics, respectively, to output pairs of new current path metrics; a current/voltage conversion circuit coupled to said second addition circuit, for converting said current path metrics calculated in said second addition circuit to voltage path metrics, a comparison and selection circuit coupled to said current/voltage conversion circuit, for comparing pairs of said voltage path metrics with each other to select path metrics having smaller path metric values which are stored in said path metric memory, and to output said path selection signals, said second addition circuit including a plurality of second common base type transistor circuits each serially connected to one of the first common base type transistor circuits.

Claim 8

An analog Viterbi decoder comprising: branch metric calculation means for successively calculating branch metrics from received symbols to output the branch metrics; adder, comparator and selector (ACS) means for successively calculating pairs of path metrics by adding preselected pairs of branch metrics and preselected pairs of last path metrics, respectively, for comparing the pairs of calculated path metrics with each other to select paths having smaller path metric values, and for outputting path selection signals to be used in said selections; and path memory means for successively storing candidates for a decoded signal according to said path selection signals and for successively refining the candidates according to said path selection signals to obtain the decoded signal, said branch metric calculation means outputting said branch metrics in analog signal form, said ACS means performing said adding, comparing, and outputting in analog signal processes, said branch metric calculation means including a current conversion circuit for converting values of said received symbols to current signals, and a first addition circuit coupled to the current conversion circuit, for calculating current branch metrics from said current signals, said ACS means including a path metric memory for storing said path metrics in voltage signal form and for outputting current path metrics, a second addition circuit coupled to said path metric memory, for adding preselected pairs of said current branch metrics and preselected pairs of said current path metrics, respectively, to output pairs of new current path metrics; a current/voltage conversion circuit coupled to said second addition circuit, for converting said current path metrics calculated in said second addition circuit to voltage path metrics, a comparison and selection circuit coupled to said current/voltage conversion circuit, for comparing pairs of said voltage path metrics with each other to select path metrics having smaller path metric values which are stored in said path metric memory, and to output said path selection signals; said comparison and selection circuit including pairs of emitter follower circuits to which pairs of said voltage path metrics are input and whose emitter terminals are connected to each other so that path metrics having smaller values are selected to be output, and differential amplifier circuits coupled to the pairs of emitter follower circuits, to which pairs of said voltage path metrics are input so that said path selection signals are output.

Claim 9

An analog Viterbi decoder comprising: branch metric calculation means for successively calculating branch metrics from received symbols to output the branch metrics; adder, comparator and selector (ACS) means for successively calculating pairs of path metrics by adding preselected pairs of branch metrics and preselected pairs of last path metrics, respectively, for comparing the pairs of calculated path metrics with each other to select paths having smaller path metric values, and for outputting path selection signals to be used in said selections; and path memory means for successively storing candidates for a decoded signal according to said path selection signals and for successively refining the candidates according to said path selection signals to obtain the decoded signal, said branch metric calculation means outputting said branch metrics in analog signal form, said ACS means performing said adding, comparing, and outputting in analog signal processes, said branch metric calculation means including a current conversion circuit for converting values of said received symbols to current signals, and a first addition circuit coupled to the current conversion circuit, for calculating current branch metrics from said current signals, said ACS means including a path metric memory for storing said path metrics in voltage signal form and for outputting current path metrics, a second addition circuit coupled to said path metric memory, for adding preselected pairs of said current branch metrics and preselected pairs of said current path metrics, respectively, to output pairs of new current path metrics; a current/voltage conversion circuit coupled to said second addition circuit, for converting said current path metrics calculated in said second addition circuit to voltage path metrics, a comparison and selection circuit coupled to said current/voltage conversion circuit, for comparing pairs of said voltage path metrics with each other to select path metrics having smaller path metric values which are stored in said path metric memory, and to output said path selection signals; said comparison and selection circuit including pairs of emitter follower circuits to which pairs of said voltage path metrics are input and whose emitter terminals are connected to each other so that path metrics having smaller values are selected to be output, and differential amplifier circuits coupled to the pairs of emitter follower circuits, to which pairs of said voltage path metrics are input so that said path selection signals are output.

Claim 10

An analog Viterbi decoder comprising: branch metric calculation means for successively calculating branch metrics from received symbols to output the branch metrics; adder, comparator and selector (ACS) means for successively calculating pairs of path metrics by adding preselected pairs of branch metrics and preselected pairs of last path metrics, respectively, for comparing the pairs of calculated path metrics with each other to select paths having smaller path metric values, and for outputting path selection signals to be used in said selections; and path memory means for successively storing candidates for a decoded signal according to said path selection signals and for successively refining the candidates according to said path selection signals to obtain the decoded signal, said branch metric calculation means outputting said branch metrics in analog signal form, said ACS means performing said adding, comparing, and outputting in analog signal processes, said branch metric calculation means including a current conversion circuit for converting values of said received symbols to current signals, and a first addition circuit coupled to the current conversion circuit, for calculating current branch metrics from said current signals, said ACS means including a path metric memory for storing said path metrics in voltage signal form and for outputting current path metrics, a second addition circuit coupled to said path metric memory, for adding preselected pairs of said current branch metrics and preselected pairs of said current path metrics, respectively, to output pairs of new current path metrics; a current/voltage conversion circuit coupled to said second addition circuit, for converting said current path metrics calculated in said second addition circuit to voltage path metrics, a comparison and selection circuit coupled to said current/voltage conversion circuit, for comparing pairs of said voltage path metrics with each other to select path metrics having smaller path metric values which are stored in said path metric memory, and to output said path selection signals; said path metric memory including two stages of sample-hold circuits.

Claim 11

An analog Viterbi decoder comprising: branch metric calculation means for successively calculating branch metrics from received symbols to output the branch metrics; adder, comparator and selector (ACS) means for successively calculating pairs of path metrics by adding preselected pairs of branch metrics and preselected pairs of last path metrics, respectively, for comparing the pairs of calculated path metrics with each other to select paths having smaller path metric values, and for outputting path selection signals to be used in said selections; and path memory means for successively storing candidates for a decoded signal according to said path selection signals and for successively refining the candidates according to said path selection signals to obtain the decoded signal, said branch metric calculation means outputting said branch metrics in analog signal form, said ACS means performing said adding, comparing, and outputting in analog signal processes, said branch metric calculation means including a current conversion circuit for converting values of said received symbols to current signals, and a first addition circuit coupled to the current conversion circuit, for calculating current branch metrics from said current signals, said ACS means including a path metric memory for storing said path metrics in voltage signal form and for outputting current path metrics, a second addition circuit coupled to said path metric memory, for adding preselected pairs of said current branch metrics and preselected pairs of said current path metrics, respectively, to output pairs of new current path metrics; a current/voltage conversion circuit coupled to said second addition circuit, for converting said current path metrics calculated in said second addition circuit to voltage path metrics, a comparison and selection circuit coupled to said current/voltage conversion circuit, for comparing pairs of said voltage path metrics with each other to select path metrics having smaller path metric values which are stored in said path metric memory, and to output said path selection signals; said path metric memory including two stages of sample-hold circuits.

Claim 12

An analog Viterbi decoder as claimed in claim 7, wherein said path metric memory includes a seesaw differential amplifier for level shifting and voltage/current conversion.

Claim 13

An analog Viterbi decoder comprising: branch metric calculation means for successively calculating branch metrics from received symbols to output the branch metrics; adder, comparator and selector (ACS) means for successively calculating pairs of path metrics by adding preselected pairs of branch metrics and preselected pairs of last path metrics, respectively, for comparing the pairs of calculated path metrics with each other to select paths having smaller path metric values, and for outputting path selection signals to be used in said selections; and path memory means for successively storing candidates for a decoded signal according to said path selection signals and for successively refining the candidates according to said path selection signals to obtain the decoded signal, said branch metric calculation means outputting said branch metrics in analog signal form, said ACS means performing said adding, comparing, and outputting in analog signal processes, said branch metric calculation means including a current conversion circuit for converting values of said received symbols to current signals, and a first addition circuit coupled to the current conversion circuit, for calculating current branch metrics from said current signals, said ACS means including a path metric memory for storing said path metrics in voltage signal form and for outputting current path metrics, a second addition circuit coupled to said path metric memory, for adding preselected pairs of said current branch metrics and preselected pairs of said current path metrics, respectively, to output pairs of new current path metrics; a current/voltage conversion circuit coupled to said second addition circuit, for converting said current path metrics calculated in said second addition circuit to voltage path metrics, a comparison and selection circuit coupled to said current/voltage conversion circuit, for comparing pairs of said voltage path metrics with each other to select path metrics having smaller path metric values which are stored in said path metric memory, and to output said path selection signals, said ACS means including a normalization circuit coupled to said path metric memory, for outputting a normalization voltage for normalizing all path metrics stored in said path metric memory, by comparing all the path metrics with each other and by selecting the smallest path metrics.

Claim 14

An analog Viterbi decoder comprising: branch metric calculation means for successively calculating branch metrics from received symbols to output the branch metrics; adder, comparator and selector (ACS) means for successively calculating pairs of path metrics by adding preselected pairs of branch metrics and preselected pairs of last path metrics, respectively, for comparing the pairs of calculated path metrics with each other to select paths having smaller path metric values, and for outputting path selection signals to be used in said selections; and path memory means for successively storing candidates for a decoded signal according to said path selection signals and for successively refining the candidates according to said path selection signals to obtain the decoded signal, said branch metric calculation means outputting said branch metrics in analog signal form, said ACS means performing said adding, comparing, and outputting in analog signal processes, said branch metric calculation means including a current conversion circuit for converting values of said received symbols to current signals, and a first addition circuit coupled to the current conversion circuit, for calculating current branch metrics from said current signals, said ACS means including a path metric memory for storing said path metrics in voltage signal form and for outputting current path metrics, a second addition circuit coupled to said path metric memory, for adding preselected pairs of said current branch metrics and preselected pairs of said current path metrics, respectively, to output pairs of new current path metrics; a current/voltage conversion circuit coupled to said second addition circuit, for converting said current path metrics calculated in said second addition circuit to voltage path metrics, a comparison and selection circuit coupled to said current/voltage conversion circuit, for comparing pairs of said voltage path metrics with each other to select path metrics having smaller path metric values which are stored in said path metric memory, and to output said path selection signals, said ACS means including a normalization circuit coupled to said path metric memory, for outputting a normalization voltage for normalizing all path metrics stored in said path metric memory, by comparing all the path metrics with each other and by selecting the smallest path metrics.

Claim 15

An analog Viterbi decoder as claimed in claim 9, wherein said normalization circuit includes a plurality of transistors having base terminals connected to be respective path metrics and having emitter terminals connected with each other to output the smallest path metric.

Claim 16

An analog Viterbi decoder as claimed in claim 9, wherein said normalization circuit includes two-stages of sample-hold circuits and said normalization voltage is supplied to the output of the second stage of said sample-hold circuits in said path metric memory.

Claim 17

An analog Viterbi decoder as claimed in claim 11, wherein said normalization voltage is supplied to an input of the first stage of said sample-hold circuit in said path metric memory.

Claim 18

An analog Viterbi decoder comprising: branch metric calculation means for successively calculating branch metrics from received symbols to output the branch metrics; adder, comparator and selector (ACS) means for successively calculating pairs of path metrics by adding preselected pairs of branch metrics and preselected pairs of last path metrics, respectively, for comparing the pairs of calculated path metrics with each other to select paths having smaller path metric values, and for outputting path selection signals to be used in said selections; and path memory means for successively storing candidates for a decoded signal according to said path selection signals and for successively refining the candidates according to said path selection signals to obtain the decoded signal, said branch metric calculation means outputting said branch metrics in analog signal form, said ACS means performing said adding, comparing, and outputting in analog signal processes, said branch metric calculation means including a current conversion circuit for converting values of said received symbols to current signals, and a first addition circuit coupled to the current conversion circuit, for calculating current branch metrics from said current signals; and a common current mirror circuit including at least one constant current source, coupled to at least one of said branch metric calculation means, said ACS means and said path memory means, for supplying at least one current to at least one of said branch metric calculation means, said ACS means and said path memory means for use in calculating the decoded signal, said current mirror circuit being coupled to a power source, and at least one constant current of said current mirror circuit varying in response to a voltage variation of the power source.

Claim 19

An analog Viterbi decoder comprising: branch metric calculation means for successively calculating branch metrics from received symbols to output the branch metrics; adder, comparator and selector (ACS) means for successively calculating pairs of path metrics by adding preselected pairs of branch metrics and preselected pairs of last path metrics, respectively, for comparing the pairs of calculated path metrics with each other to select paths having smaller path metric values, and for outputting path selection signals to be used in said selections; and path memory means for successively storing candidates for a decoded signal according to said path selection signals and for successively refining the candidates according to said path selection signals to obtain the decoded signal, said branch metric calculation means outputting said branch metrics in analog signal form, said ACS means performing said adding, comparing, and outputting in analog signal processes, said branch metric calculation means including a current conversion circuit for converting values of said received symbols to current signals, and a first addition circuit coupled to the current conversion circuit, for calculating current branch metrics from said current signals; and a common current mirror circuit including at least one constant current source, coupled to at least one of said branch metric calculation means, said ACS means and said path memory means, for supplying at least one current to at least one of said branch metric calculation means, said ACS means and said path memory means for use in calculating the decoded signal, said current mirror circuit being coupled to a power source, and at least one constant current of said current mirror circuit varying in response to a voltage variation of the power source.

Claim 20

An analog Viterbi decoder supplied with received symbols, comprising: branch metric calculation means for successively calculating branch metrics from received symbols to output the branch metrics; adder, comparator and selector (ACS) means for successively calculating pairs of path metrics by adding preselected pairs of branch metrics and preselected pairs of last path metrics, respectively, for comparing the pairs of calculated path metrics with each other to select paths having smaller path metric values, and for outputting path selection signals to be used in said selections; and path memory means for successively storing candidates for a decoded signal according to said path selection signals and for successively refining the candidates according to said path selection signals to obtain a decoded signal, said path memory means including a first stage path memory part having n-stages of path memory cells for receiving said path selection signals, and for providing n-bit output signals; a digital/analog conversion part coupled to the first stage path memory part, for converting the n-bit output signals from said n-stages of path memory cells to analog signals, an analog path memory part coupled to the digital/analog conversion unit and having a plurality of stages of analog path memory cells, for sequentially storing said analog signals, and an encoder coupled to the first-stage path memory part and the analog path memory part, for supplying selection signals corresponding to said path selection signals to said analog path memory part every time n path selection signals are input.

Claim 21

An analog Viterbi decoder supplied with received symbols, comprising: branch metric calculation means for successively calculating branch metrics from received symbols to output the branch metrics; adder, comparator and selector (ACS) means for successively calculating pairs of path metrics by adding preselected pairs of branch metrics and preselected pairs of last path metrics, respectively, for comparing the pairs of calculated path metrics with each other to select paths having smaller path metric values, and for outputting path selection signals to be used in said selections; and path memory means for successively storing candidates for a decoded signal according to said path selection signals and for successively refining the candidates according to said path selection signals to obtain a decoded signal, said path memory means including a first stage path memory part having n-stages of path memory cells for receiving said path selection signals, and for providing n-bit output signals; a digital/analog conversion part coupled to the first stage path memory part, for converting the n-bit output signals from said n-stages of path memory cells to analog signals, an analog path memory part coupled to the digital/analog conversion unit and having a plurality of stages of analog path memory cells, for sequentially storing said analog signals, and an encoder coupled to the first-stage path memory part and the analog path memory part, for supplying selection signals corresponding to said path selection signals to said analog path memory part every time n path selection signals are input.